A5077471241- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Optical Network Technologies
- Advanced Photonic Communication Systems
- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Semiconductor materials and devices
- Thin-Film Transistor Technologies
- Advanced MEMS and NEMS Technologies
- Semiconductor Quantum Structures and Devices
- Advanced Memory and Neural Computing
- Advanced Optical Network Technologies
- Integrated Circuits and Semiconductor Failure Analysis
- Force Microscopy Techniques and Applications
- Optical Wireless Communication Technologies
- VLSI and Analog Circuit Testing
- Geophysics and Sensor Technology
- Microwave Engineering and Waveguides
- Semiconductor materials and interfaces
- Radiation Effects in Electronics
- Adhesion, Friction, and Surface Interactions
- Advanced Fiber Laser Technologies
- Analog and Mixed-Signal Circuit Design
- Mechanical and Optical Resonators
NTT (Japan)
2011-2023
The University of Tokyo
2006-2010
NTT Basic Research Laboratories
2008-2009
A burst-mode clock and data recovery circuit (CDR) for 10 G-EPON systems is described. We propose a new architecture with single gated voltage-controlled oscillator (GVCO), digital frequency detector, ΔΣ digital-to-analog converter (DAC). The GVCO detector reduce error to less than 2 MHz. DAC eliminates external devices. Moreover, the simulation results show more tolerant process, voltage, temperature (PVT) variations conventional charge pump. fabricated test CDR this using 0.25 μm SiGe...
The CDR circuit is fabricated in 0.25 mum SiGe BiCMOS technology. low-speed digital blocks, such as the frequency detector, up/down counter, modulator, and dither generator, are developed using CMOS transistors. LPF used DAC integrated chip. Two power supplies, 3.3 V for bipolar transistors 1.8 CMOS, used. PONs 10G-EPON systems require a burst-mode upstream transmission that has an instantaneous response, tolerance to long consecutive-identical digits (CIDs), high jitter tolerance. In this...
In burst transmission systems such as passive optical networks (PONs), a burst-mode CDR circuit must be able to retime and reshape the input data. this paper, is presented that achieves output-data-jitter reduction of 3dB at jitter frequency 1GHz, synchronization data within 14 bits input, tolerance pulse-width distortion (PWD) +0.22/−0.32UI 10.3125Gb/s operation. These characteristics are provided by architecture with jitter-reduction PWD-compensation circuits.
This paper describes a 56-Gb/s transimpedance amplifier with level-shift circuit and double-feedback-loop (DFB) compensation architecture to achieve high input sensitivity. The placed between main post mitigates the trade-off bandwidth noise of receiver, which reduces referred by 70%. DFB compensates for process variation without increasing noise. was fabricated in 0.13-um SiGe BiCMOS technology packaged an avalanche photodiode. 3-dB 38.4 GHz current density 14.8 pA/rtHz are achieved. These...
The range of communication services can be significantly expanded if an optical network unit (ONU) is driven by laser energy via fiber. One use case in this context driving ONU for collecting sensor data from IoT devices environment without a power supply (e.g., mountain), but single-mode fiber only about 1 / 1000 the required typical ONU. We therefore developed power-saving algorithm. Experiments with prototyped showed that average consumption was reduced to (15 mW) and it could at our...
Get PDF Email Share with Facebook Tweet This Post on reddit LinkedIn Add to CiteULike Mendeley BibSonomy Citation Copy Text Y. Ohtomo, H. Kamitsuna, Katsurai, K. Nishimura, M. Nogawa, Nakamura, S. Nishihara, T. Kurosaki, Ito, and A. Okada, "High-speed circuit technology for 10-Gb/s optical burst-mode transmission," in Optical Fiber Communication Conference, OSA Technical Digest (CD) (Optica Publishing Group, 2010), paper OWX1. Export BibTex Endnote (RIS) HTML Plain alert Save article
A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. symmetric topology makes the area for GVCO smaller leads to an easier timing design. The consists of two loops that operate complementarily. Circuit configurations same type are adopted AND OR in reduce difficulties alignment signals from loops. To confirm validity proposed topology, we fabricated BCDR IC with 65-nm-MOSFET process. It can extract 12.5-GHz...
A burst-mode CDR (B-CDR) suffers from a trade-off between jitter transfer and lock time. To solve the trade-off, we utilize continuous-mode (C-CDR) after B-CDR with converting burst signal to quasi-continuous by idle insertion. The B-CDR, designed in 40-nm CMOS, also employs fully digital, 6-bit automatic frequency calibrator for compensating process variation. It calibrates oscillation of VCO 10.3 GHz ± 2 60 MHz. integrated C-CDR, achieves output-data-jitter reduction 17.3 dB at 300 MHz...
Newly developed dual-rate OLT and ONU SoCs combined with our latest transceivers demonstrate high efficient 10G/1G simultaneous discovery processing hardware-accelerated dynamic bandwidth allocation of the transmission time according to requirements.
This article describes a burst-mode receiver that is key component of 0 Gigabit Ethernet passive optical network (0G-EPON) systems.In addition to coping with burst signal, the can operate at data rates both 0.325 and .25 Gbit/s meet need for coexistence future 0G-EPON existing PON (GE-PON) units.The sensitivities are -30.3 -35.6 dBm Gbit/s, respectively, when settling time 400 ns.These results GE-PON specifications sufficient margins.
Newly developed dual-rate OLT and ONU SoCs combined with our latest transceivers demonstrate high efficient 10G/1G simultaneous discovery processing hardware-accelerated dynamic bandwidth allocation of the transmission time according to requirements.
A low-power compact 4-channel transmitter consisting of a 65-nm CMOS cascode shunt LD driver and flip-chip-bonded 1.3-μm LD-array-on-Si achieves 25-Gbps 2-km-long SSMF error-free operation for each channel, with power consumption 1.37 mW/Gbps.
A 25Gbit/s-class burst-mode receiver for 50G-EPON systems with a 25G APD and TIA, fabricated by 0.13-μm SiGe BiCMOS technology, achieves record high sensitivity of -27.7 dBm (OMA) at BER=10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> settling time 150 ns.
As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. conventional (GE-PON) systems have already widely deployed, 1G/10G co-existence technologies are strongly required for next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented It employs two new circuits to improve jitter transfer provide tolerance operation. An injection-controlled...
A 12.5-Gb/s burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. symmetric topology makes the area for GVCO smaller leads to an easier timing design. The consists of two loops which operate complementarily. same type configurations are adopted AND OR in reduce difficulties alignment signals from loops. To confirm validity proposed topology, we fabricated 12.5-Gb/s-BCDR IC with 65-nm-MOSFET process. Without precise...
We developed a practical high-sensitivity 10-Gbit/s III-V compound-based avalanche photodiode (APD), and an receiver optical subassembly (ROSA) mounting the APD for burst-mode operation. The features inverted p-down structure with 200-nm InAlAs layer that produces low excess noise dark current simultaneously at large gain. By combining our trans-impedance amplifier (B-TIA), resulting APD-ROSA exhibited -32.7 dBm signals, which allows loss budget exceeding 35 dB on access networks such as...
We propose a low-power millimeter-wave ultra-wideband impulse radio (UWB-IR) transmitter using an on/off keying (OOK) pulse modulator for wireless connection or dielectric-waveguide interconnects. To achieve consumption, we use OOK consisting of only four CMOS inverters and passive elements. The proposed was fabricated in 65-nm technology. It exhibits the maximum data rate 8 Gbps, output power -15.6 dBm, consumption 20.1 mW, efficiency 2.5 mW/Gbps at operating frequency 50 GHz.
We propose a new model that can accurately estimate the maximum output electrical power of an optical supply system with low input power. The includes dependence open-end voltage on proposed is compared conventional ignores dependency. Our shows significantly decreases as becomes weak.
This paper proposes a new electrostatic impact drive actuator that is operated by DC high voltage. In the actuator, movable mass oscillates between two opposing electrodes such it alternately collides against electrodes. The collisions are converted into locomotion unique design of electrode supports. actuation principle characterized its simple structure, which would facilitate applications in special environments or miniaturization actuator. operation modeled using an equivalent electric...
A 25-Gb/s low-power Clock and Data Recovery (CDR) with Clocked CMOS (C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> MOS) D-Flip-Flop (D-FF) for low power operation is presented. In a CDR circuit, D-FF one of the dominant factor on consumption. this work, we design 25-GHz clock by using C MOS D-FF. reduces 84 % compared conventional current mode logic (CML) To validate proposed design, fabricated in 65-nm process. The area core...
We developed high-power SOA integrated EADFB lasers (AXEL) and a high-sensitivity burst-mode receiver with an avalanche photodiode (APD) to ensure the loss budget in transmission line extend reach for 10G- 25G-PON (35 word limit)