The burst-mode 3R receiver using monolithic ICs for 10-Gbit/s-class optical access networks is reported. In a point-to-multipoint system like passive network (PON), the at line terminal (OLT) must be able to handle packets with significantly different powers and phases. An OLT high sensitivity instantaneous response burst inputs desired widening accommodation area efficiency in PON uplinks. Currently, diffusion of high-speed Internet connection services represented by fiber home 1.25 Gbit/s...

In this paper, we propose a multistage transimpedance amplifier (TIA) based on the local negative feedback technique. Compared with conventional global-feedback technique, proposed TIA has advantages of wider bandwidth, and lower power dissipation. The schematic characteristics circuit are described. Moreover, employs inductive peaking to increase bandwidth. is implemented using 65 nm complementary metal oxide semiconductor (CMOS) technology consumes 23.9 mW supply voltage 1.0 V. Using...

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the sources of emitter-coupled-logic (ECL) series gate circuits are removed lower differential pairs controlled by circuits. This enables with same function as two-stacked ECL to operate at -2.0 V reduces drawn through driving 50% conventional level shift (emitter followers) in ECL. CMCL achieves 3.1-Gb/s (D-FF) 4.3-GHz (T-FF) operation a power...

A loop parameter optimization method for a phase-locked (PLL) used in wide area networks (WANs) is proposed as technique achieving good jitter characteristics. It shown that the characteristics of PLL, especially transfer and generation, depend strongly on key /spl zeta//spl omega//sub n/ (/spl zeta/ damping factor natural angular frequency PLL), focusing dependence make it possible to comprehensively determine parameters filter constants PLL will fully comply with ITU-T specifications....

A burst-mode PIN-TIA module has been developed using SiGe BiCMOS technology and successfully operated at 10.3 Gbit/s with an instantaneous response of 10 ns, a high sensitivity −19.5 dBm wide dynamic range 20.5 dB.

Regression and classification are necessary for biometric systems carried out using machine learning. A method regression is long short-term memory (LSTM). We proposed implemented algorithms low-energy LSTM the of microwave-sensor signals into a small-scale FPGA. found that our FPGA-based parallel (including unrolled)-pipelined algorithm decreased computation time by 95% compared with sequential algorithm. In addition, amount energy consumption was reduced 92% 91% high-end GPU CPU, respectively.

A multi-rate burst-mode clock and data recovery (BCDR) circuit based on a simple gated voltage-controlled oscillator (GVCO) is presented. symmetric topology makes the area for GVCO smaller leads to an easier timing design. The consists of two loops that operate complementarily. Circuit configurations same type are adopted AND OR in reduce difficulties alignment signals from loops. To confirm validity proposed topology, we fabricated BCDR IC with 65-nm-MOSFET process. It can extract 12.5-GHz...

A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated Si bipolar technology. The output jitter characteristics of CDR can be controlled by designing loop-gain design switched-filter PLL technique. used in local-area networks (LANs) long-haul backbone or wide-area (WANs). Its power consumption only 0.4 W. For LANs, generation when gain optimized 1.2 ps (0.003 UI). for WANs meet all three types STM-I6 specifications given ITU-T...

A design technique for an over-10-Gb/s clock and data recovery (CDR) IC provides good jitter tolerance low jitter. To the CDR using a PLL that includes decision circuit with certain phase margin affecting pull-in performance, we derived simple expression range of PLL, which call "limited range," used it performance evaluation. The method allows us to quickly easily compare conventional full-rate half-rate clock, verified is advantageous because its wider frequency range. For verification...

This paper describes a jitter suppression technique for 2.48832-Gb/s clock and data recovery (CDR) circuit that uses phase-locked loop (PLL). decreases the generation improves transfer function. Jitter is suppressed by boosting gain in PLL. A suitable function tolerance achieved using low-center-frequency (f/sub c/) surface acoustic wave (SAW) filter. The fabricated has low [about 2.4 mUI rms (below 1 ps rms)] cutoff frequency of (about 500 kHz) as result SAW filter with f/sub c/ 622.08 MHz....

DOI: 10.1049/ic:20070170 ISBN: 978-3-8007-3042-1 Location: Berlin, Germany Conference date: 16-20 Sept. 2007 Format: PDF A 10 G burst-mode PIN-TIA module has been developed with a new function of automatic offset compensation. An instantaneous response ns, high sensitivity -19.5 dBm, and wide dynamic range 20.5 dB were obtained. (2 pages) Inspec keywords: optical communication equipment; fibre communication; high-speed techniques Subjects: Optical devices, equipment systems; Ultrafast

A new phase-backed loop (PLL) with a simple architecture that overcomes the trade-off problem between acquisition time and phase noise was fabricated in 0.2 µm CMOS process. One-fifth of integer-N is achieved by switching only division ratio optimised damping factor to control natural frequency.

A laser-diode (LD) driver with interwoven mutually-coupled peaking inductors for high-speed optical networks is presented. Six and four are into two sets of area-effective implementation as well performance enhancement. The proposed circuit fabricated in CMOS 0.18-μm process. area 0.34mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> the maximum operating speed 16Gbps. Compared to a conventional LD CMOS, achieves 1.6 times faster...

This paper discusses bandwidth enhancement technique for high speed amplifier. Inductive peaking is a common practice enhancement, however the area occupied by on-chip inductors heavy disadvantage. We utilize mutually coupled effective inductive peaking. A Laser-Diode (LD) driver optical communication system designed in 0.18μm CMOS. Measurement results show that inductor can achieve 16Gbps operation and 26% reduction compared to conventional shunt

We present an area-efficient and low-power four-channel 25-Gb/s trans-impedance amplifier for Rx analog front-end (Rx-AFE) on optical receiver. The proposed circuit features a local negative-feedback (TIA) to expand the bandwidth. TIA post-amplifier use regulated cascode (RGC) topology two differential stages with inductive peaking bandwidth extension technique acquire 19.6 GHz of -3 dB 53.3 dBΩ gain. designed system using 65-nm CMOS process, Rx-AFE TIAs achieved small area 300 µm × 800 per...

An electric power conversion system constructed by connecting two or more converters in parallel is advantageous for achieving large capacity and standardization. In this paper, the control method cross current when three are operated examined, reexamined as a preferable construction method.

In-vehicle optical network systems have been studied eagerly for realizing self-driving cars. To provide a stable operation of the receiver in system, we propose an appropriate-time-constant control circuit burst-mode transimpedance amplifier (TIA) which provides adaptive response single-ended to differential conversion accordance with input-data patterns. We present operating principles, design procedures, and post-layout simulation results proposed 65-nm CMOS process. verify fast within 4...

If two or more Permanent Magnet Synchronous Motors (PMSM) can be controlled by one inverter, a train driven less energy than the present Induction Motor (IM) drive system. First, this paper proposes method for simulating movement of wheels and vehicle to develop control method. Next, is presented controlling PMSMs inverter.

10G burst-mode PIN-TIA module has been developed using a fast two-stage AOC technique. It exhibits quick response of 10 nsec, high sensitivity of-19.5 dBm, and wide dynamic range 20.5 dB.

We present a novel burst-mode transimpedance amplifier (TIA) with gain-mode switching. The proposed TIA utilizes regulated-cascode (RGC) input stage for broadband characteristics. To expand dynamic range, the RGC controls linear operating range depending on gains by adjusting bias conditions. This is implemented using 0.18µm-CMOS technology. experimental results show that IC has good eye-opening and can respond quickly to burst data.

This paper describes a simple routing control system. We propose achieving high-speed data transmission without modifying the frame configuration. To add signal, called "labeling signal" in this paper, to frame, we use frequency modulation technique on transmitted frame. means you need not change when transmit additional signals. Using prototype system comprising field-programmable gate array and discrete elements, investigate performance devise method achieve high resolution. A...

Recently, self-driving cars have been eagerly studied and developed. In such applications, to transmit large-capacity data acquired by sensor devices as radars, LiDARs, high-definition cameras, optical fiber networks are promising intra-vehicle systems. One type of network has a unidirectional ring topology, in which the receiver operates burst mode. this paper, we demonstrate an adaptive time-constant-control circuit that enables quick response signal high tolerance large consecutive...

Co-packaged optics (CPO) modules have been studied and developed for improving data capacity reducing power consumption of data-center optical communications. In this paper, we present a 16-channel receiver circuit multicore fiber (MCF)-based CPO module in single 65-nm CMOS chip. This chip consists circuits, received signal strength indicators (RSSIs) power-supply noise filters photo detectors. Characteristics the fabricated using process were evaluated by on-wafer probing, clear eye...