A5025064617- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon and Solar Cell Technologies
- Nanowire Synthesis and Applications
- Semiconductor materials and interfaces
- Ion-surface interactions and analysis
- Ferroelectric and Negative Capacitance Devices
- Thin-Film Transistor Technologies
- nanoparticles nucleation surface interactions
- Advanced Surface Polishing Techniques
- Microstructure and mechanical properties
- Aluminum Alloy Microstructure Properties
- 3D IC and TSV technologies
- Physics of Superconductivity and Magnetism
- Silicon Carbide Semiconductor Technologies
- Advanced Memory and Neural Computing
- Metal and Thin Film Mechanics
- Crystallography and Radiation Phenomena
- Acoustic Wave Resonator Technologies
- Aluminum Alloys Composites Properties
- Advanced Materials Characterization Techniques
- Laser Material Processing Techniques
- Electronic and Structural Properties of Oxides
- Surface and Thin Film Phenomena
Soitec (France)
2007-2020
Universidade Estadual de Campinas (UNICAMP)
2020
Forschungszentrum Jülich
2012-2013
STMicroelectronics (France)
2009-2010
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2010
CEA LETI
2010
Université Grenoble Alpes
2010
Institut polytechnique de Grenoble
2010
CEA Grenoble
2010
Alcatel Lucent (Germany)
1999-2000
In this letter, we report the performance of high-κ /metal gate nanowire (NW) transistors without junctions fabricated with a channel thickness 9 nm and sub-15-nm length NW width. Near-ideal subthreshold slope (SS) extremely low leakage currents are demonstrated for ultrascaled lengths high on-off ratio (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ) >; 10 <sup...
Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by segregation at low temperatures improve band-to-band tunneling, resulting in higher on-currents n- and p-TFETs > 10 μA/μm <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub...
Sources responsible for local and inter-die threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> ) variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack are experimentally discriminated the first time. Charges dielectric and/or TiN workfunction fluctuations determined as major contributors to V it is found that SOI thickness (T xmlns:xlink="http://www.w3.org/1999/xlink">Si</inf> variations have...
We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local intrinsic V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -variability performances are obtained (A xmlns:xlink="http://www.w3.org/1999/xlink">VT</sub> =1.45mV.μm). This leads to 6T-SRAM cells with good characteristics down xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.5V supply voltage excellent...
Guided by the Wentzel-Kramers–Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters Si TFETs are presented and experimentally verified. Along this line, improvements achieved implementation of uniaxial strain in nanowires (NW), benefits high-k/metal gates, newly engineered junctions as well effect scaling NW to diameters 10 nm demonstrated. Specifically, self-aligned ion implantation into source/drain silicide dopant segregation has been exploited achieve...
Using an advanced 300mm CMOS-platform, we report record-low and highly-uniform propagation loss: 0.45±0.12dB/cm for wires, 2dB/cm slot waveguides. For WDM devices, demonstrate channel variation(3-σ) within-wafer within-device of 6.1nm 1.2nm respectively.
We present gate all around strained Si (sSi) nanowire array TFETs with high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> (64μA/μm at V xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =1.0V). Pulsed I-V measurements provide small SS and record xmlns:xlink="http://www.w3.org/1999/xlink">60</sub> of 1×10 <sup xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> μA/μm 300K due to the suppression trap assisted tunneling (TAT)....
For the first time, Multi-V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> UTBOX-FDSOI technology for low power applications is demonstrated. We highlight effectiveness of back biasing short devices in order to achieve I xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> current improvement by 45% LVT options at an xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> 23nA/µm and a leakage reduction 2 decades HVT one. In addition, fully...
Strain analysis of complex three-dimensional nanobridges conducted via Raman spectroscopy requires careful experimentation and data supported by simulations. A method combining micro-Raman with finite element is presented, enabling a detailed understanding strain-sensitive measured on Si nanobridges. Power-dependent measurements are required to account for the priori unknown scattering efficiency related size geometry. The experimental used assess validity previously published phonon...
We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (<2 nm) gate oxides in sub-30 nm effective channel length nMOSFETs. The peak an nMOSFET was observed at t/sub ox//spl ap/1.3 for a 1.5 V power supply voltage with T/sub n//spl ap/0.7, while the pMOSFET ap/1.5 -1.5 p//spl ap/0.5. Since carrier scattering is due predominately to interface roughness, reducing transverse surface field, either by or increasing oxide thickness, can be used...
We study the implant-induced hydrogenated defects responsible for Smart Cut™ layer transfer of Si (001) films. Different experimental methods are used to quantify time dependence defect evolution and interactions during isothermal annealings. An optical characterization technique was developed statistical analysis formation growth micrometer size microcracks in buried implanted layer. show that molecular hydrogen is dominated by a transient phenomenon related rapid dissociation point...
This letter presents experimental results on tunneling field-effect transistors featuring arrays of Ω-gated uniaxially strained and unstrained silicon nanowires. The gate control a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /poly-Si stack is compared with high- <i xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal stack. Steep inverse subthreshold slopes down to 76 mV/dec relatively high on-currents were achieved the...
This paper presents a comprehensive simulation study of the process and statistical variability in 16-nm technology node bulk silicon-on-insulator (SOI) fin field effect transistors (FinFETs). The devices are carefully designed to offer good manufacturability while meeting performance requirements technology. First, sensitivity two types FinFETs process- induced channel length, fin-width, fin-height is investigated compared based on threshold voltage, OFF-current, overdrive current...
In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual oxide co-integrated devices EOT 17 ¿/V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> 1.1 V 29 1.8 are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term Multiple Vt achievement matching improvement. Delay improvement up to 15% on Ring Oscillators compared bulk 45 nm...
Extended defects formed after hydrogen implantation into Si and Ge (100) substrates subsequent thermal anneals were investigated by transmission electron microscopy. The majority of the extended in both materials platelet-like structures lying on {100} {111} planes. We found platelets not only parallel but also perpendicular to surface. In wafers, high density {311} nanobubbles with average size 2 nm observed. difference between two can be attributed weaker strength Ge–H bond.
For the first time, we demonstrate low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> (V xmlns:xlink="http://www.w3.org/1999/xlink">Tlin</sub> ±0.32V) nMOS and pMOS adjusted in a gate FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune above midgap while maintaining good reliability...
The integration of lanthanum lutetium oxide (LaLuO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ) with a n value 30 is, for the first time, demonstrated on strained and unstrained SOI n/p-MOSFETs as gate dielectric full replacement process. LaLuO /Si interface showed very thin silicate/SiO xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interlayer D xmlns:xlink="http://www.w3.org/1999/xlink">it</sub> level 4.5 × 10 <sup...
Silicon implanted with boron at 1015 cm−2 dose and energies from 500 eV to 1 keV were annealed over wide variations in temperature time obtain process kinetics thermal activation for shallow junction formation. Diffusion depths carrier densities determined by modeling sheet electrical transport. The energy the mean produce is found be 5.1±0.1 eV, while diffusivity it 4.1±0.1 eV. difference expresses quantitatively particular advantage of spike anneals temperatures above 1000 °C.