A5019193677- Semiconductor materials and devices
- Plasma Diagnostics and Applications
- Phase-change materials and chalcogenides
- Advanced Memory and Neural Computing
- Metal and Thin Film Mechanics
- Advancements in Photolithography Techniques
- Copper Interconnects and Reliability
- Liquid Crystal Research Advancements
- Chalcogenide Semiconductor Thin Films
- Advancements in Semiconductor Devices and Circuit Design
- Advanced MEMS and NEMS Technologies
- Diamond and Carbon-based Materials Research
- Ferroelectric and Negative Capacitance Devices
- Magnetic properties of thin films
- Force Microscopy Techniques and Applications
- Block Copolymer Self-Assembly
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Surface Polishing Techniques
- Electronic Packaging and Soldering Technologies
- Nanofabrication and Lithography Techniques
- Electronic and Structural Properties of Oxides
- Transition Metal Oxide Nanomaterials
- Nanowire Synthesis and Applications
- Electron and X-Ray Spectroscopy Techniques
- 3D IC and TSV technologies
IBM Research - Thomas J. Watson Research Center
2011-2025
Franche-Comté Électronique Mécanique Thermique et Optique - Sciences et Technologies
2001-2022
IBM (United States)
2010-2021
United States Naval Research Laboratory
2021
University of Virginia
2020
University of Illinois Urbana-Champaign
2020
National Taiwan University of Science and Technology
2020
University of Maryland, College Park
2020
Amrita Vishwa Vidyapeetham
2020
Université de franche-comté
2001-2019
We discuss novel multi-level write algorithms for phase change memory which produce highly optimized resistance distributions in a minimum number of program cycles. Using integration scheme, test array at 4 bits/cell and 32 kb page 2 are experimentally demonstrated.
The etching of Si, SiO2, Si3N4, and SiCH in fluorocarbon plasmas is accompanied by the formation a thin steady-state film at substrate surface. thickness this etch rate have often been related. In present work, has characterized for wide range processing conditions high-density plasma reactor. It was found that not necessarily main parameter controlling rate. When varying self-bias voltage, example, we weak correlation between thickness. Instead, conditions, it ion-induced defluorination...
The authors demonstrate atomic layer etching of SiO2 using a steady-state Ar plasma, periodic injection defined number C4F8 molecules, and synchronized plasma-based Ar+ ion bombardment. enables control the deposited fluorocarbon (FC) thickness in one to several Ångstrom range chemical modification surface. For low energy bombardment conditions, physical sputter rate vanishes, whereas can be etched when FC reactants are present at have measured for first time temporal variation chemically...
Directed self-assembly (DSA) of lamellar phase block-co-polymers (BCPs) can be used to form nanoscale line-space patterns. However, exploiting the potential this process for circuit relevant patterning continues a major challenge. In work, we propose way impart two-dimensional pattern information in graphoepitaxy-based DSA processes by utilizing interactions BCP with template pattern. The image formation mechanism is explained through use Monte Carlo simulations. Circuit patterns consisting...
The need for atomic layer etching (ALE) is steadily increasing as smaller critical dimensions and pitches are required in device patterning. A flux-control based cyclic Ar/C4F8 ALE on steady-state Ar plasma conjunction with periodic, precise C4F8 injection synchronized plasma-based low energy Ar+ ion bombardment has been established SiO2 [Metzler et al., J. Vac. Sci. Technol. 32, 020603 (2014)]. In this work, the process further characterized extended to of silicon under similar conditions....
An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) through (3nm) films; the GeSb material offers potential both fast crystallization and good data retention
We have successfully demonstrated a novel "pore" phase change memory cell, whose critical dimension (CD) is independent of lithography. Instead, the pore diameter accurately defined by intentionally creating "keyhole" with conformal deposition. Fully integrated 256 kbit test chips been fabricated in 180nm CMOS technology. report SET times 80ns, RESET currents less than 250μA, and accurate sub-lithographic CDs that can be 20% size lithographically -defined diameter.
In this paper, we report the first demonstration of CMOS-integrated racetrack memory. The devices measured are complete memory cells integrated into back end line IBM 90 nm CMOS. We show good integration yield across 200 mm wafers. With magnetic field-assist, demonstrate current-driven read and write operations on within a 256-cell array.
A three-terminal spin-torque-driven magnetic switch is experimentally demonstrated. The device uses nonlocal spin current and accumulation as the main mechanism for current-driven switching. It separates current-induced write operation from that of a tunnel junction based read. only passes through metallic structures, improving reliability. structure makes efficient use lithography capabilities, important robust process integration.
Phase change memory has long suffered from conflicting material properties between switching speed and thermal stability. This study explores the engineering of GeSbTe ternary alloys along an isoelectronic tie line Ge/Sb <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> Te xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> with hope finding a high performance material. Our efforts resulted in new that considerably outperforms conventional...
BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-4] are integrated in large (512 × 1024) arrays at 100% yield, and successfully co-integrated together with Phase Change Memory (PCM). Numerous desirable attributes demonstrated: the currents (>;200μA) needed for PCM, bipolar operation required high-performance RRAM, single-target sputter deposition essential high-volume manufacturing, ultra-low leakage ( 10 pA) high voltage margin (1.5V) to enable crosspoint arrays.
We present the fabrication of sub-20 nm nanopores and nanopore arrays in membranes with embedded multilayer electrodes using CMOS semiconductor processes.
BEOL-friendly Access Devices (AD) based on Cu-containing MIEC materials [1-3] are shown to scale the <;30nm CDs and <;12nm thicknesses found in advanced technology nodes. Switching speeds at high (>100uA) currents of NVM writes can reach 15ns; reads typical (~5uA) current levels be ≪1usec.
Several attractive applications call for the organization of memristive devices (or other resistive non-volatile memory (NVM)) into large, densely-packed crossbar arrays. While resistive-NVM frequently possess some degree inherent nonlinearity (typically 3–30× contrast), operation large ( 1000×1000 device) arrays at low power tends to require quite 1e7) ON-to-OFF ratios (between currents passed high and voltages). One path such nonlinearities is inclusion a distinct access device (AD)...
Abstract Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable strategy capable producing chips designs down single-digit nanometre dimensions over 200 mm wafer scale. Compatible semiconductor industry standard complementary metal-oxide logic circuit processes, this extracts patterned sacrificial silicon layer through hundreds...
We provide a status report on the development of perovskite-based transition-metal-oxide resistance-change memories. focus bipolar resistance switching observed in Cr-doped SrTiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> memory cells with dimensions ranging from bulk single crystals to CMOS integrated nanoscale devices. also discuss electronic and ionic processes during electroforming switching, as evidenced electron-parametric...
We demonstrate the world's first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small 3 nm. NW capacitance shows size dependence in good agreement that of a cylindrical capacitor. AC characterization enhanced self-heating below 5
Application of phase change memory (PCM) has been limited by the high power required to reset device (changing from crystalline amorphous state melting material). Utilizing poor thermal and electrical conductivity TaN we have designed a simple structure that thermally insulates bottom electrode thus drastically reduces heat loss. A 39nm with barrier 1.5nm TiN conductor demonstrated 30µA current, representing 90% reduction. The benefit insulation is understood through electrothermal...
The ability to achieve atomic layer etch precision is reviewed in detail for a variety of material sets and implementation methods. For cyclic approach most similar reverse ALD scheme, the process window truly self-limited (ALE) identified limitations as function controlling adsorption step, irradiation energy, reaction are examined. Alternative approaches, namely processes enable pseudo-ALE precision, then introduced results from their application investigated. Most recent work plasma...
The authors demonstrate that complex hydrofluorocarbon (HFC) precursors offer significant advantages relative to gas mixtures of comparable elemental ratios for plasma-based selective atomic layer etching (ALE). This work compares a fluorocarbon precursor and H2 with an HFC precursor, i.e., octafluorocyclobutane (C4F8) 3,3,3-trifluoropropene (C3H3F3), SiO2 ALE Si3N4 or Si. For continuous plasma etching, process mixtures, e.g., C4F8/H2, have been employed enable highly material removal based...
A manufacturable platform of CMOS, RF and opto-electronic devices fully PDK enabled to demonstrate a 4×25 Gb/s reference design is presented. With self-aligned fiber attach, this technology enables low-cost O-band data-com transceivers. In addition, can offer enhanced performance yield in hybrid-assembly for applications at 25 Gbaud beyond.
With the increasing interest in establishing directional etching methods capable of atomic scale resolution for fabricating highly scaled electronic devices, need development and characterization layer processes, or generally etch processes with precision, is growing. In this work, a flux-controlled cyclic plasma process used SiO2 Si at Angstrom-level. This based on steady-state Ar plasma, periodic, precise injection fluorocarbon (FC) precursor (C4F8 CHF3) synchronized, plasma-based Ar+ ion...
A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. current-confining structure leads to a self-heating at the center of chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900μA 75nm diameter multilevel operation are reported
We describe a cycling failure mode in Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Sb Te xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> -based phase change memory, based on density difference of GST different phases and the SET/RESET thermal operations. Voids that develop merge with each other within programming volume after eventually lead to cell failure. By adding suitable amount doping material into GST, we are able delay...