We demonstrate Ge0.95Sn0.05 p-channel gate-all-around field-effect transistors (p-GAAFETs) with sub-3 nm nanowire width (WNW) on a GeSn-on-insulator (GeSnOI) substrate using top-down fabrication process. Thanks to the excellent gate control by employing an aggressively scaled structure, p-GAAFETs exhibit small subthreshold swing (SS) of 66 mV/decade, decent on-current/off-current (ION/IOFF) ratio ∼1.2 × 106, and high-field effective hole mobility (μeff) ∼115 cm2/(V s). In addition, we also...

New doping techniques are needed for the formation of abrupt, ultrashallow junctions with high concentration in source/drain or extension regions metal-oxide-semiconductor field-effect transistors (MOSFETs) at advanced technology nodes. In addition, 3-D device structures, such as fin transistors, require a good conformality. this paper, monolayers silicon on InGaAs by disilane silane treatment surface is studied conformal dopant source that does not introduce ion implant damage into InGaAs,...

The structural, compositional, and electrical properties of epitaxial Ni4InGaAs2 (denoted as Ni-InGaAs) film formed by annealing sputtered Ni on InGaAs were investigated. It was found that Ni-InGaAs adopts a NiAs (B8) structure with lattice parameters = 0.396 ± 0.002 nm c 0.516 nm, exhibits an relationship InGaAs, orientations given Ni-InGaAs[1¯10]//InGaAs[001] Ni-InGaAs[110]//InGaAs[110]. has bulk resistivity ∼102 μΩ·cm, which increases the thickness scales below 10 nm. results this work...

Damping constant ξ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FE</sub> is the key parameter that determines maximum operating speed of negative capacitance ferroelectric field-effect transistor (NC-FET). While most studies assume a specific material, in this letter, we propose method to extract value which dependent on its polarization. This applies both Miller model (positive capacitance) and Landau (negative capacitance). It enables...

We report a novel common gate stack solution for Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-x</sub> Sn xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> P-MOSFET and In xmlns:xlink="http://www.w3.org/1999/xlink">0.7</sub> Ga xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> As N-MOSFET, featuring sub-400°C Si xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> H xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> passivation, sub-1.3...

The fabrication and characterisation of a gate‐first In 0.7 Ga 0.3 As channel Π‐gate junctionless transistor by CMOS‐compatible top‐down approach is reported for the first time. structure uses simple layer process flow. 3D device simulation shows that can deplete carriers more effectively compared with planar tri‐gate devices. fabricated 200 nm gate length good transfer characteristics I on / off ratio ∼10 4 subthreshold swing ∼210 mV/decade. results indicate suitability proposed operation.

For the first time, complementary FinFETs and tunneling (TFFETs), with fin width (WFin) of 20 nm height (Hfin) 50 nm, were co-integrated on same substrate, enabled by formation high-quality GeSn-on-insulator (GeSnOI) substrate 200 mm wafer size. Decent electrical characteristics realized for both GeSn n-and p-channel TFFETs. We also performed simulation studies to show promise GeSnOI platform, which is not only able suppress off-state leakage current improve Ion/Ioff ratio FETs, but can...

In this work, novel hybrid circuits based on metal–oxide–semiconductor field-effect transistors (MOSFETs) and negative-capacitance (NC-FETs) were proposed for analog circuit applications, including operational transconductor amplifier (OTA) single-ended to the differential converter. We focus design innovation take advantage of effect negative resistance (NDR) in NC-FETs. It was found that a significant increase output ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML"...

We report the demonstration of Ge0.97Sn0.03 P-MOSFETs, featuring low temperature Si2H6 passivation, HfO2 high-k dielectric and TaN metal gate. P-MOSFET with high drive current negligible hysteresis was realized. NBTI characterization performed to investigate off-leakage, suthreshold swing, peak transconductance degradation threshold voltage shift under stress. Excellent device reliability characteristics were observed.

We realized the first germanium-tin (GeSn) gate-alI-around (GAA) p-channel field-effect-transistors (p-FETs) on a 200 mm GeSn-on-insulator (GeSnOI) substrate, achieving subthreshold swing (SS) of 74 mV/ decade for device with channel length (LCH) 60 nm. The GAA structure provided excellent control short effects and also enabled realization transistor LCH 20 nm decent electrical characteristics.

A novel technique for doping the source/drain or extension regions of InGaAs MOSFETs was developed based on silane treatment and laser anneal. This has potential to provide conformal, ultra-shallow, very abrupt n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">++</sup> junctions while being free from implant damage, is first demonstrated in planar MOSFETs.

Ultrashallow junctions that are abrupt and have low resistance needed for the source/drain extensions (SDEs) of MOSFETs at future technology nodes. In addition, use 3-D devices, such as FinFETs or nanowire FETs, will require a doping process is conformal. this paper, we discuss P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> S xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> /(NH xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> )...

We report the first GeSn p-FinFETs with sub-10 nm fin width (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fin</sub> ) enabled by formation of 200 mm GeSn-on-insulator (GeSnOI) substrate and a self-limiting digital etch for accurate control dimension, achieving top 5 nm. Owing to excellent gate using extremely scaled good quality maintained device fabrication process low thermal budget, an SS 63 mV/decade was achieved at channel length (L...

2-D simulations were performed to compare the drive currents of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with self-aligned contact metallization and those non-self-aligned in order determine importance InGaAs MOSFETs at advanced technology nodes. A gate length 15 nm was simulated, various gap...

A lateral bandgap engineered floating body cell (FBC) memory is demonstrated for the first time; it features a high-k gate dielectric, metal gate, and an epitaxially grown Si <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.99</inf> C xmlns:xlink="http://www.w3.org/1999/xlink">0.01</inf> S/D. Design of valence band offset incorporation strain effects are achieved from heterogeneously mismatched lattice S/D regions. The figures merit in FBC...

Strained silicon-on-insulator (SSOI) is a promising platform for 5G, which will require both high-performance and low-power complementary metal-oxide- semiconductor (CMOS) devices. Hence, it important to understand the behavior of strain in SSOI at deeply scaled dimensions. We thus present simulation study technology, where profiles “fins” with different dimensions layer thicknesses are analyzed. discover, first time, that buried oxide (BOX) as thin 10-15 nm able effectively memorize strain....

For the first time, ion implant was used to partially relax tensile strain by half in fully-depleted (FD) strained SOI (SSOl) so that SiGe pFETs with a higher compressive can be realized at fixed Ge composition. This enables co-integration of highly tensile-strained Si nFETs and compressive-strained on same substrate, achieving significant improvement electrical performance over unstrained counterpart verified both experiment simulation results. We also propose Comb-like architecture further...

We report the demonstration of a new contact resistance reduction technology for Si:C S/D using Tellurium (Te) implant and segregation. When integrated in novel process flow featuring single-metal platinum-based silicide (PtSi) technology, independent control SBH n- p-FinFETs can be achieved. A low electron 120 meV is attained n-FinFETs with PtSi Te segregation, giving an I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dsat</sub> enhancement...

The relaxation of tensile strain in fully depleted (FD) strained silicon-on-insulator (SSOI) by means ion implantation is experimentally demonstrated this work. This could enable SiGe p-channel field-effect transistors (pFETs) with high compressive (after and Ge condensation) to be formed together Si n-channel (nFETs) on the same substrate. From simulations advanced technology node, 0.8% nFETs -0.9% pFETs fin structures can provide saturation drain current peak G <sub...

We investigate a solid state reaction between Ge and Ni–InGaAs on n + In 0.53 Ga 0.47 As its effects the contact resistance of Ni-based contacts InGaAs. This was performed by isochronous annealing at temperatures ranging from 400 to 600 °C in N 2 ambient. It found that regrown InGaAs layer rich formed below metal contact. Compared with contact, more than 60% reduction Si-implanted n-In achieved after °C. structure characterized secondary ion mass spectroscopy, high resolution transmission...

We investigate a solid state reaction between Ge and Ni–InGaAs on n+ In0.53Ga0.47As its effects the contact resistance of Ni-based contacts InGaAs. This was performed by isochronous annealing at temperatures ranging from 400 to 600 °C in N2 ambient. It found that regrown InGaAs layer rich formed below metal contact. Compared with contact, more than 60% reduction Si-implanted n-In0.53Ga0.47As achieved after °C. structure characterized secondary ion mass spectroscopy, high resolution...

In the first part of this two-part article, implant-induced strain relaxation has been successfully demonstrated on a common strained silicon-on-insulator (SSOI) platform. second part, based an SSOI platform that could enable cointegration highly tensile-strained Si n-channel field-effect transistors (nFETs) and compressive-strained SiGe p-channel FETs (pFETs) same substrate for both logic 5G RF circuits, we here propose comb-like device structure within SOI further improvement in...