A5100729078- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Silicon Carbide Semiconductor Technologies
- Nanowire Synthesis and Applications
- Advanced Thermoelectric Materials and Devices
- Semiconductor materials and interfaces
- Force Microscopy Techniques and Applications
- Silicon Nanostructures and Photoluminescence
- Thin-Film Transistor Technologies
- Low-power high-performance VLSI design
- Thermal properties of materials
- Ion-surface interactions and analysis
- Photonic and Optical Devices
- Metal and Thin Film Mechanics
- Radiation Effects in Electronics
- Advanced Memory and Neural Computing
- Advanced Surface Polishing Techniques
- Electrostatic Discharge in Electronics
- Semiconductor Quantum Structures and Devices
- Thermal Radiation and Cooling Technologies
- Optical Network Technologies
- GaN-based semiconductor devices and materials
- Silicon and Solar Cell Technologies
National Institute of Advanced Industrial Science and Technology
2012-2021
Ashikaga University
2020
Waseda University
1992-2017
Meiji University
2010-2017
Japan Society for the Promotion of Science
2017
Ibaraki National College of Technology
2006
University of Tsukuba
2004
Mitsubishi Electric (Japan)
1975-2003
Japan Science and Technology Agency
2003
Okayama University
2002
We report on a path-independent insertion-loss (PILOSS) 8 × matrix switch based Si-wire waveguides, which has record-small footprint of 3.5 2.4 mm2. The PILOSS consists 64 thermooptic Mach-Zehnder (MZ) switches and 49 low-crosstalk intersections. Each the MZ intersections employs directional couplers, enable composition low loss switch. demonstrate successful switching digital-coherent 43-Gbps QPSK signal.
This paper describes a comprehensive study on the threshold voltage (V/sub th/) controllability of four-terminal-driven double-gate (DG) MOSFETs (4T-XMOSFETs) with independently switched DGs. Two types 4T-XMOSFETs (fin and vertical) are experimentally demonstrated their V/sub th/ is thoroughly investigated in relation to initial DG-mode based comprehensible modeling devices. Based investigation simulated predictions, device design guidelines for proposed. Decreasing workfunction DGs...
We propose a planar device architecture compatible with the CMOS process technology as optimal current benchmark of Si-nanowire (NW) thermoelectric (TE) power generator. The proposed is driven by temperature gradient that formed in proximity perpendicular heat flow to substrate. Therefore, unlike conventional TE generators, short Si-NWs need not be suspended on cavity structure. Under an externally applied difference 5 K, recorded density observed 12 μm/cm <sup...
The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels FinFETs by using conventional reactive sputtering. It was found that TiN (phi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TiN</sub> ) slightly decreases increasing nitrogen (N xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gas flow ratio, R xmlns:xlink="http://www.w3.org/1999/xlink">N</sub>...
Variability of TiN FinFET performance is comprehensively studied. It found that the variation in occurs and standard deviations nMOS pMOS FinFETs are almost same. From analytical results, it due to work function (WFV) metal gate. The WFV also responsible for on-current variation.
In this letter, we propose a synthetic electric field (SE) effect to enhance the performance of tunnel field-effect transistors (TFETs). The novel SE-TFET architecture utilizes both horizontal and vertical fields induced by gate electrode that is wrapped around an ultrathin epitaxial channel. drain current increased up 100 times in comparison with those conventional TFETs. subthreshold slope also improved, enhanced 52 mV/decade scaling channel width thickness.
Ultrashort-channel junctionless FETs (JL-FETs) were fabricated on silicon-on-insulator substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching. The channel length, defined as the width of V-groove bottom, was short 3 nm, and thickness between 1 8 nm. Excellent transistor characteristics with threshold voltages that are optimal for low-power operation obtained both n-FETs p-FETs when gate dielectric film reduced to origin excellent electrostatic control is...
For harvesting energy from waste heat, the power generation densities and fabrication costs of thermoelectric generators (TEGs) are considered more important than their conversion efficiency because heat is essentially obtained free charge. In this study, we propose a miniaturized planar Si-nanowire micro-thermoelectric generator (SiNW-μTEG) architecture, which could be simply fabricated using complementary metal–oxide–semiconductor–compatible process. Compared with conventional nanowire...
Hf0.5Zr0.5O2 thin films are not always ferroelectric. This work investigates the impact of annealing temperature and time on crystalline structures dielectric properties 10 nm thick films. It is found that tetragonal phase crystal formed from amorphous film firstly, then transforms to orthorhombic monoclinic phases, in accordance with time. The volume fraction film, which known as origin ferroelectricity, becomes dominant a certain range condition. Thus, responsible for anti-ferroelectric,...
Amorphous TaSiN metal gates (MGs) are successfully introduced in FinFETs to suppress work function variation (WFV) of the MG, which is a dominant contributor threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> ) variability undoped channel MG FinFETs. Comparing with poly-crystalline TiN gate, gate reduces V drastically and records smallest A xmlns:xlink="http://www.w3.org/1999/xlink">Vt</inf> value 1.34 mVμm reported so...
A fully integrated step-up dc-dc converter for energy harvesting applications is presented. minimum start-up voltage of 100 mV achieved by the mechanism based on an LC oscillator (LCO). Conventional converters with LCO-based provide a significantly low conversion efficiency around 1%. To overcome this drawback, following two circuit techniques are proposed in brief: 1) gate-boosted charge pump; and 2) LCO deactivation. The fabricated 65-nm silicon-on-thin-buried-oxide process. measurement...
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Cointegration of titanium nitride (TiN)-gate high-performance tied-gate three-terminal FinFETs with symmetric gate-oxide thicknesses <formula formulatype="inline"><tex>$(t_{{\rm ox}1} = t_{{\rm ox}2} \hbox{1.7}\ \hbox{nm})$ </tex></formula> and variable threshold-voltage formulatype="inline"><tex>$V_{\rm th}$</tex></formula> independent-gate four-terminal (4T) asymmetric (<formula...
A vertical ultrathin channel formation process for a type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also that the ion-bombardment-retarded (IBRE) independent of species and implanted impurities can easily transferred dopants source drain regions MOSFETs. By utilizing IBRE, DG MOSFETs with 12-nm-thick were fabricated successfully. The clearly exhibit unique...
We fabricated hafnium carbide (HfC) coated Si field emitter arrays (HfC FEAs) with an extraction-gate electrode to improve the emission characteristics of FEAs. Hafnium thin film was deposited by inductively coupled plasma-assisted magnetron sputtering. The HfC characterized x-ray photoelectron spectroscopy and diffraction measurement, found be (111)-oriented polycrystalline film. FEAs exhibited superior performance. An more than 10 mA could obtained from 16 000 tip array, which is 20 times...
SRAM cells with V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> -controllable independent double-gate (IDG) FinFETs have been successfully fabricated. The performance of the fabricated cell various circuit topologies has investigated comprehensively. Both a reduction leakage current and an enhancement read write noise margins demonstrated by introducing IDG into cells.
The V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> variability in scaled FinFETs with gate length (L xmlns:xlink="http://www.w3.org/1999/xlink">g</inf> ) down to 25 nm was systematically investigated, for the first time. By investigating oxide thickness (T xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf> dependence of variation (VTV), gate-stack origin, i.e., work-function (WFV) and charge (Q (OCV) origin VTV were successfully...
ON-current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) variability is comprehensively investigated for fin-shaped FETs (FinFETs) by measurement-based analysis. Variation sources of I are successfully extracted as independent contributions threshold voltage V xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> , transconductance G xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> and parasitic resistance R...
Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade very low off-currents (on the order a few pA/μm) have been experimentally realized on Si CMOS platform. Improvements in SSs by optimizing epitaxial channel growth heavily arsenic- boron-doped source surfaces for purging interface defects at junctions. By improving quality, 58 56 on/off current ratios (ON/OFF) 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This brief presents an ultralow-power wake-up receiver using ultrasound for Internet of Things applications. To achieve both high sensitivity and low power consumption, we propose a Colpitts-oscillator-based super-regenerative (COSR). Owing to the simple architecture proposed COSR, lowest supply voltage operation 0.3 V smallest area are achieved. Furthermore, consumption is scalable determined by input signal data rate, which configurable user. In field test, wakeup consumes 1 μW, smaller...
A high aspect ratio and damage-free vertical ultrathin channel for a vertical-type double-gate MOSFET was fabricated by using low-energy neutral-beam etching (NBE). NBE can completely eliminate the charge build-up photon-radiation damages caused plasma. The FinFETs realize higher device performance (i.e., electron mobility) than that obtained conventional reactive-ion etching. improved mobility is well explained NB-etched atomically flat surface. These results strongly support effectiveness...
The nanoscale wet etching of physical-vapor-deposited (PVD) titanium nitride (TiN) and its application to sub-30-nm-gate-length fin-type double-gate metal–oxide–semiconductor field-effect transistor (FinFET) fabrication are systematically investigated. It is experimentally found that PVD-TiN side-etching depth can be controlled one-half thickness with precise time control using an ammonium hydroxide (NH 4 OH) : hydrogen peroxide (H 2 O ) deionized water O) = 1 5 solution at 60 °C. Using the...
An independent-double-gate (IDG) fin-type MOSFET (FinFET) SRAM has been successfully fabricated with considerable leakage current reduction. The new consists of IDG-FinFETs which have flexible <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> controllability. IDG-FinFET a TiN metal gate is by newly developed gate-separation etching process. By appropriately controlling the IDG-FinFET, we...
We propose a p-channel bilayer TFET composed of an n-type oxide semiconductor (n-OS)/p-type group-IV (p-IV) heterostructure, allowing us to realize both n- and operations under the same device structure. Here, p-IV side in heterostructure has metal-oxide-semiconductor (MOS) gate-stack that modulates surface potential MOS interface controls band-to-band tunneling (BTBT) current p-TFET operation. Technology computer-aided design (TCAD) simulation predicts operation with symmetric electrical...