The current-induced perpendicular magnetic anisotropy tunnel junctions (p-MTJs) offer a number of advantages, such as high density and speed. As p-MTJs downscale to ~40 nm, further performance enhancements can be realized thanks spin-torque efficiency, i.e., lower critical current higher thermal stability. In this paper, we investigate the origin efficiency give phenomenological theory describe reduction due subvolume activation. Based on various physical theories structural parameters,...

Conventional complementary metal-oxide semiconductor (CMOS)-based devices are approaching their physical limits to continue the Moore's law. Spintronic that exploit intrinsic spin freedom of electron in addition its fundamental electrical charge show great potential nanoscale technology nodes. In particular, hybrid spintronic/CMOS based on magnetic tunnel junctions (MTJs) has been considered as a very promising approach thanks high speed, low power, good scalability and full compatibility...

3-D technology that stacks silicon dies with through vias (TSVs) is a promising solution to overcome the interconnect scaling problem in giga-scale integrated circuits (ICs). Thermal dissipation major challenge for integration and prior thermal-balanced task scheduling methods multiprocessor system-on-chips (MPSoCs) typically balance power gradient across vertical based on assumption of strong thermal correlation among processing cores within stack. On other hand, MPSoCs employ...

Spin-transfer torque magnetic random access memory (STT-RAM) is a promising and emerging technology due to its many advantageous features such as scalability, nonvolatility, density, endurance, fast speed. However, the operation of STT-RAM severely affected by environmental factors process variations temperature. As temperature rockets up in modern computing systems, it highly desirable understand thermal impact on operations reliability. In this paper, thermal-aware MTJ model, calibrated...

Spin transfer torque magnetic random access memory (STT-MRAM) possesses many desirable properties such as nonvolatility, fast speed, unlimited endurance, and good compatibility with CMOS fabrication process. ITRS has highlighted the potential of STT-MRAM one candidates for next-generation universal technology. However, both behaviors Magnetic Tunnel Junction (MTJ) transistor, which are two basic elements STT-MRAM, generally temperature dependent, threatening reliability, performance under...

Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access (MRAMs) have potential mitigate shortcomings. Moreover, it is predicted that they could be used for DRAM SRAM replacement. However, are prone manufacturing defects runtime failures as any other type memory. This article provides an up-to-date practical...

In this article, we propose a carbon nanotube (CNT) field-effect transistor (CNFET)-based static random access memory (SRAM) design at the 5-nm technology node that is optimized based on tradeoff between performance, stability, and power efficiency. addition to size optimization, physical model parameters including CNT density, diameter, CNFET flat band voltage are evaluated for SRAM performance improvement. Optimized compared with state-of-the-art 7-nm FinFET cell Arizona State University...

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising emerging technology due to its various advantageous features such as scalability, nonvolatility, density, endurance, and fast speed. However, the reliability of STT-MRAM severely impacted by environmental disturbances because radiation strike on transistor could introduce potential write read failures for 1T1MTJ cells. In this paper, comprehensive approach proposed evaluate radiation-induced soft errors spanning...

The STT-MRAM technology is a promising candidate for future on-chip cache memory because of its high density, low standby power, and nonvolatility. As the node scales, especially under 40-nm node, cell design becomes key issue to approach power consumption, access performance, desirable reliability. conventional 1T-1 magnetic tunnel junction (MTJ) 2T-2MTJ designs cannot address these challenges efficiently. In this paper, we propose novel 3T-3MTJ structure using advanced perpendicular MTJ...

We propose a multi-corner multi-stage timing analysis prediction framework using generalized linear model with latent features. then further improve such methods kernel trick extension, transfer learning knowledge from previous designs, and multi-output feature engineering to deliver state-of-the-art (SOTA) accuracy very limited training data. Most importantly, our method is equipped Bayesian decision strategy reliable predictions close 100%, pushing the frontier of machine-learning-based...

Due to its non-volatility, high access speed, ultra low power consumption and unlimited writing/reading cycles, STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) has emerged as the most promising candidate for next generation universal memory. However, process of commercialization is hampered by poor reliability. Generally, these reliability issues are caused PVT (Process Variations, Voltage, Temperature) both MTJ (Magnetic Tunneling Junction) transistor. Mitigation alleviating...

Spin transfer torque magnetic random access memory (STT-MRAM) is a potential candidate for next generation universal technology, which possesses the high density and cost benefits of DRAM, speed SRAM, non-volatility Flash, compatibility with CMOS essentially unlimited endurance. However, STT-MRAM commercialization hampered by reliability issues, especially its poor thermal reliability. Generally, elevated ambient temperature Joule heating cause issues STT-MRAM. These effects result in many...

The size and parameter optimization for the 5-nm carbon nanotube field effect transistor (CNFET) static random access memory (SRAM) cell was presented in Part I of this article. Based on that work, we propose a (CNT) SRAM array composed schematically optimized CNFET CNT interconnects. We consider interconnects inside metallic single-wall (M-SWCNT) bundles to represent metal layers 0 1 (M0 M1). investigate layout structure considering devices, M-SWCNT interconnects, electrode Palladium with...

In modern advanced integrated circuit design, a design normally needs to be progressively optimized until the static timing analysis (STA) of full process corners meets constraints. To improve efficiency, using machine learning predict path timings directly in order reduce extensive time-consuming SPICE simulations has become promising technique approach fast closure. However, current methods lack both flexibility and reliability used practical industrial environment. resolve these...

Multilevel spin toque transfer RAM (STT-RAM) is a suitable storage device for energy-efficient neural network accelerators (NNAs), which relies on large-capacity on-chip memory to support brain-inspired large-scale learning models from conventional artificial networks current popular deep convolutional networks. In this paper, we investigate the application of multilevel STT-RAM general-purpose NNAs. First, error-resilience feature leveraged tolerate read/write reliability issue in cell...

Considering the insatiable demand for high-performance computing, on-chip cache capacity increases rapidly. Spin-transfer-torque magnetoresistive random-access memory (STT-MRAM) is a promising candidate due to ultralow standby power, high-access speed, and integration density. Unfortunately, when feature size of magnetic tunnel junction (MTJ) scales down 1 Xnm, read current approaches write closely, which may result in disturbance threatening reliability STT-MRAM. Furthermore, elevating...

As the integration density rockets up for contemporary VLSI circuits, power consumption limits scalability of technology advancement CMOS. Spin transfer torque-magnetic random access memory (STT-MRAM), as one emerging non-CMOS technologies, has promising prospect low standby power, fast speed and compatibility with CMOS fabrication process. However, node scaling down, typical 1 Transistor-1 Magnetic Tunnel Junction (1T-1MTJ) STT-RAM cell suffers from severe reliability challenges, especially...

Spin transfer torque magnetic random access memory (STT-MRAM) is currently under intensive investigation for one of the possible alternatives to extend Moore's Law beyond CMOS technology scaling limit. Its advantageous features, such as nonvolatility, high speed, low power and excellent scalability etc, attract worldwide R&D attention. However scales (e.g., below 40 nm), process variations introduce big read reliability challenges STT-MRAM due reduced sensing margin (SM) increased...

Three dimensional (3D) System-on-Chips (SoCs) that typically employ through-silicon vias (TSVs) as vertical interconnects, emerge a promising solution to continue Moore's law. Whereas, it also brings challenging problems, one of which is the test wrapper chain design and optimization, especially for circuit-partitioned 3D SoCs in scan chains can cross among layers. Test time primary goal design, both 2D SoCs. The SoC problem be converted into well-studied2D by projecting components all...