A5057661896- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Low-power high-performance VLSI design
- Analog and Mixed-Signal Circuit Design
- Sepsis Diagnosis and Treatment
- Trauma and Emergency Care Studies
- Trauma Management and Diagnosis
- Integrated Circuits and Semiconductor Failure Analysis
- Radio Frequency Integrated Circuit Design
- Cardiac Arrest and Resuscitation
- Advancements in PLL and VCO Technologies
- Photonic and Optical Devices
- Advanced Memory and Neural Computing
- Neural Networks and Applications
- Immune Response and Inflammation
- CCD and CMOS Imaging Sensors
- Mechanical Circulatory Support Devices
- Abdominal Trauma and Injuries
- Trauma, Hemostasis, Coagulopathy, Resuscitation
- Hemodynamic Monitoring and Therapy
- Traumatic Brain Injury and Neurovascular Disturbances
- Pelvic and Acetabular Injuries
- Quantum-Dot Cellular Automata
- Nosocomial Infections in ICU
- Advanced Glycation End Products research
Chiba Hokusou Hospital
2010-2022
Nippon Medical School
1994-2016
Tsukuba Medical Center Hospital
2009-2012
Semiconductor Energy Laboratory (Japan)
2006-2007
Mitsubishi Electric (Japan)
1987-2005
Mitsubishi Electric (Germany)
1984-2003
Mitsubishi Group (Japan)
1984-2002
National Disaster Medical Center
1997
Laboratoire des Sciences de l’Information et de la Communication
1997
Kitamurayama Hospital
1997
Resuscitative endovascular balloon occlusion of the aorta (REBOA) is one ultimately invasive procedures for managing a noncompressive torso injury. Since it less than resuscitative open aortic cross-clamping, its clinical application expected.We retrospectively evaluated safety and feasibility REBOA (intra-aortic balloon, MERA, Tokyo, Japan) using Seldinger technique to control severe hemorrhage. Of 5,230 patients admitted our trauma center in Japan from 2007 2013, we included 24 who...
This article evaluates the suitability of cadavers embalmed by saturated salt solution (SSS) method for surgical skills training (SST). SST courses using have been performed to advance a surgeon's techniques without any risk patients. One important factor improving is specimens, which depends on embalming method. In addition, infectious and cost involved in are problems that need be solved. Six were 3 methods: formalin solution, Thiel (TS), SSS methods. Bacterial fungal culture tests...
A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, developed. This architecture enables one to convert a pair of partial products in normal (NB) form RE number with no additional circuit. We improved RB adder (RBA) circuit so that it can make addition products. also simplified converter converts final into corresponding NE number. The carry propagation path carried out only multiplexer circuits. 54/spl times/54-bit multiplier designed...
This paper describes a new leading-zero anticipatory (LZA) logic for high-speed floating-point addition (FADD). carries out the pre-decoding normalization concurrently with significand. It also performs shift operation of in parallel rounding operation. The use simple Boolean algebra allows proposed to be constructed from CMOS circuit. Its area penalty is as small 30% conventional LZA method. FADD core using was fabricated by 0.5 /spl mu/m technology triple metal interconnections and runs at...
An error checking and correcting (ECC) technique that checks multiple cell data simultaneously allows fast column access is described. The ECC circuit optimized with respect to the increase in chip area access-time penalty, can be applied a 16-Mbit DRAM 20% less penalty. soft rate has been estimated about 100 times smaller than of basic horizontal-vertical parity-code technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Aim Senior surgeons in Japan who participated “cadaver‐based educational seminar for trauma surgery ( CESTS )” subsequently stated their interest seminars more difficult procedures. Therefore, we held a 1‐day advanced‐ with saturated salt solution SSS )‐embalmed cadavers and assessed its effectiveness surgical skills training SST ). Methods Data were collected from three carried out September 2015 to January 2018, including 10‐point self‐assessment of confidence levels SACL ) questionnaire...
A self-learning neural network chip based on the branch-neuron-unit (BNU) architecture, which expands scale of a by interconnecting multiple chips without reducing performance, is described. The integrates 336 neurons and 28224 synapses with 1.0- mu m double-poly-Si double-metal CMOS technology. operation speed higher than 1*10/sup 12/ connections per second chip. It estimated that can be expanded to several hundred chips. In case 200-chip interconnections, will consist 3360 5,644,800...
We identify possible differences in the cytokine/chemokine profiles cerebrospinal fluid (CSF) from children with encephalopathy and febrile seizure. Interleukin (IL)-1beta, 2, 4, 5, 6, 7, 8, 10, 12, 13, 17, interferon-gamma, tumour necrosis factor-alpha, granulocyte colony-stimulating factor, monocyte chemoattractant protein-1 macrophage inflammatory protein-1beta were measured simultaneously CSF supernatants (n = 8), seizure 16) fever without neurological complications 8). IL-8 was...
Background: The healing process of bone fracture requires a well-controlled multistage and sequential order beginning immediately after the injury. However, complications leading to nonunion exist, creating serious problems costs for patients. Transforming growth factor-beta 1 (TGF-β1) morphogenic protein 2 (BMP-2) are two major factors involved in human by promoting various stages ossification. In this study, we aimed determine role these during long bones assess their impacts on condition....
A 1.9 GHz IF transceiver for the Japanese standard personal handy-phone system (PHS) is fabricated in a 0.8-/spl mu/m BiCMOS process with 20 npn. down-mixer, up-mixer, variable attenuator, quadrature modulator, first and second PLL, VCO are included 3.4/spl times/3.0 mm/sup 2/ chip. The chip draws 24 mA receive mode 44 transmit mode, operating from 3.0 V. total vector error of 4% /spl pi//4 QPSK PN9 pattern includes up-mixer dual PLLs.
A learning neural network LSI chip is described. The integrates 125 neuron units and 10K synapse with the 1.0 mu m double-poly-Si, double-metal CMOS technology. Most of this integration has been realized by using a mixed design architecture digital analog circuits. fully feedback connection can memorize at least 15 patterns 50 s time for each pattern. Under condition that test vector keeps Hamming distance 6 from memorized pattern, correct association rate 98% obtained. relaxation 1 to 2 s....
Aim In Japan, trauma surgery training remains insufficient, and on‐the‐job has become increasingly difficult because of the decreasing number severe patients development non‐operative management. Therefore, we assessed whether a 1‐day cadaver‐based seminar is effective for training. Methods Data were collected from 11 seminars carried out January 2013 to March 2014, including 10‐point self‐assessment confidence levels ( SACL ) 21 surgical skills an evaluation contents before, just after,...
This study investigated the advantages of performing urgent resuscitative surgery (URS) in emergency department (ED); namely, our URS policy, to avoid a delay hemorrhage control for patients with severe torso trauma and unstable vital signs. We divided 264 eligible cases into group (n = 97) non-URS 167) compare, retrospectively, observed survival rate predicted using Trauma Injury Severity Score (TRISS). While revised score injury severity were significantly lower than group, was higher...
This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new gate has smaller intrinsic delay time than conventional gates. Furthermore, this rail-to-rail output voltage. Therefore the next does not have large degradation of its driving capability. exclusive OR and NOR using shows speed advantage over CMOS gates under wide variance in load capacitance. were applied to full adders, path circuits, select circuits. In consequence, was fabricated...
We present a 64 b Carry Look-ahead (CLA) adder having 2.6 ns delay time at 3.3 V power supply within 0.27 mm/sup 2/ using 0.5 /spl mu/m CMOS technology. derived its structure from considering the tradeoffs between speed and area. This consideration includes not only gate intrinsic but also wiring capacitance delay. Moreover we introduced new carry select scheme called Modified Select (MCS). MCS has 20% area advantage over conventional Adder (CSA).
In the prehospital setting, it is difficult to use Glasgow Coma Scale (GCS) evaluate consciousness state using in pediatric patients with severe trauma. The Japan (JCS) a scale used widely and, its four grades, simpler and quicker than GCS. This study examined whether JCS can predict clinical traumatic brain injury (TBI) outcome aged 3 15 years setting.
The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field transistors (SOI MOSFET's) were investigated. Here, "substrate bias" is the body bias SOI MOSFET itself. It was found that transistor becomes fully depleted released from effect, when reverse-biased. Moreover, it voltage for reverse-bias as high zero-bias. This phenomenon analyzed using a three-dimensional (3-D) device simulation considering...
A 0.18 /spl mu/m silicon on insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology using hybrid trench isolation with high resistivity substrate is proposed and its feasibility for embedded RF/analog applications demonstrated. The a combination of partial full isolation. In the region, part SOI layer remains under field oxide so as to provide scalable body-tied metal-oxide-semiconductor field-effect transistors (MOSFETs), while in whole replaced by quality passives. It...
An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, combination of hierarchical data bus configuration and multipurpose register (MPR) provides high-speed access. The MPR also includes practical array-embedded error checking correcting (ECC) little area penalty no overhead in page mode. applied to scaled-down 16-Mb DRAM has achieved high performance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We have designed, fabricated and measured a second-order multibit switched-capacitor complex bandpass ΔΣAD modulator to evaluate our new algorithms architecture. propose structure of filter in the forward path with I, Q dynamic matching, that is equivalent conventional one but can be divided into two separate parts. As result, AS modulator, which employs proposed also parts, there are no signal lines crossing between upper lower paths formed by filters feedback DACs. Therefore, layout design...
This paper presents a high speed 64-b floating point (FP) multiplier that has useful function for computer graphics (CG). The critical path delay is minimized by using logic gates and limiting the stage number of series transmission (TGs). redundant binary architecture applied to multiplication significands. FP special "CG multiplication" directly multiplies pixel data an data. was fabricated 0.5-/spl mu/m CMOS technology with triple-level metal interconnection. active area size 4.2/spl...
To improve the density of BiCMOS sea-of-gates, bipolar and PMOS transistors are merged to form compact basic cells combined with gate isolation technique. This structure occupies only 12% conventional transistor area. The cell increases by 60% compared cells. pull-up circuit achieves fastest delay 200 ps. A 16-bit multiplier in test chip fabricated 0.8 mu m technology operates at 18 ns time.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
A 4Mb DRAM employing a folded-bitline adaptive sidewall - isolated capacitance cell with 2μm deep trenches, 72.3mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip size and 90ns access time will be described. Also incorporated are full bonding options for 4Mb×1 or 1Mb×4 organizations static column page-mode operation.