A5043518947- Advanced Memory and Neural Computing
- Magnetic properties of thin films
- Quantum and electron transport phenomena
- Neural Networks and Applications
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- Parallel Computing and Optimization Techniques
- Low-power high-performance VLSI design
- Numerical Methods and Algorithms
- Advancements in Semiconductor Devices and Circuit Design
- Radiation Effects in Electronics
- Ferroelectric and Negative Capacitance Devices
- CCD and CMOS Imaging Sensors
- Quantum Computing Algorithms and Architecture
- Interconnection Networks and Systems
- Magnetic Field Sensors Techniques
- Silicon and Solar Cell Technologies
- VLSI and Analog Circuit Testing
ShanghaiTech University
2021-2025
University of California, San Diego
2025
Shanghai Institute of Microsystem and Information Technology
2022
University of Chinese Academy of Sciences
2022
Abstract Neuromorphic diffusion models have become one of the major breakthroughs in field generative artificial intelligence. Unlike discriminative that been well developed to tackle classification or regression tasks, aim at creating content based upon contexts learned. However, more complex algorithms these result high computational costs using today’s technologies. Here, we develop a spintronic voltage-controlled magnetoelectric memory hardware for neuromorphic process. The in-memory...
This paper presents the temperature-dependent characterizations and compact modeling on both front-end-of-line (FEOL) back-end-of-line (BEOL) devices based HLMC 40-nm low-power CMOS technology. Moreover, an EDA-compatible cryo-CMOS platform which covers 10 region is developed to guide design of specific cryogenic integrated circuits for quantum computing applications.
This paper reports an 8-bit current steering-type cryogenic digital-to-analog converter (DAC) module using HLMC 40nm low-power (40LP) technology for fast qubit initialization in quantum computers. Based on the generic design platform generated from our cryo-CMOS compact model, we optimize circuit to ensure its correct function with temperature-insensitive non-linearity. Benefiting integration of nA-range on-chip reference and appropriate gate sizing, a low power consumption 13.8 $\mu$W under...
This brief introduces a read bias circuit to improve readout yield of magnetic random access memories (MRAMs). A dynamic optimization (DBO) is proposed enable the real-time tracking optimal voltage across MRAM process variations and operating temperature fluctuation within an array. It optimizes performance by adjusting dynamically for maximum sensing margin. Simulation results on 28-nm 1Mb macro show that accuracy DBO remains above 90% even when varies up 50%. Such strategy further in two...
Stochastic diffusion processes are pervasive in nature, from the seemingly erratic Brownian motion to complex interactions of synaptically-coupled spiking neurons. Recently, drawing inspiration Langevin dynamics, neuromorphic models were proposed and have become one major breakthroughs field generative artificial intelligence. Unlike discriminative that been well developed tackle classification or regression tasks, as other such ChatGPT aim at creating content based upon contexts learned....
We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages compensate threshold voltage (VTH) shift at low temperatures. optimized NMOS and PMOS transistors, featured by VTH<0.2V, sub-threshold swing (SS)<30 mV/dec, on-state current (Ion)>1.2mA/um 77K, warrant reliable sub-0.6V operation. Moreover, enhanced driving strength Cryo-CMOS inherited from...
This brief introduces a read bias circuit to improve readout yield of magnetic random access memories (MRAMs). A dynamic optimization (DBO) is proposed enable the real-time tracking optimal voltage across processvoltage-temperature (PVT) variations within an MRAM array. It optimizes performance by adjusting dynamically for maximum sensing margin. Simulation results on 28-nm 1Mb macro show that accuracy DBO remains above 90% even when varies up 50%. Such strategy further in two orders...