This paper presents the fastest and most energy efficient body channel communication transceiver integrated into smallest chip area. To enhance data rate with limited human bandwidth, decision feedback equalization technique is adopted to for first time. The transceiver, fabricated in 65 nm CMOS technology, reliably (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> ) achieves maximum rates of 150 Mb/s 100 over 20-cm 1.0 m...

This article presents the body channel communication technique that first adopts decision feedback equalisation. For time, we characterised post-cursor intersymbol interference of a single-bit pulse response human for equalisation achieving faster than 100 Mb/s. In proposed technique, an 8-tap equaliser is utilised at receiver to compensate channel. The experimental results show prototype transceiver achieved highest data rates 150 Mb/s and 10 along 20-cm about 100-cm channels, respectively....

This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our generator automatically produces models of devices and selectors from the measured I-V data to reduce too much time consumption in manual development for simulation target circuits. To verify our method, diverse ReRAMs were generated simulated various The results show that can accurately describe original allows quantitative...

This paper disproves the worst read scenario of a ReRAM crossbar array. If previously believed is not one, margin evaluated based on can be incorrect. We explored for worse than by wisely sampling scenarios and iteratively searching one. In experiment, our algorithm successfully found disproving scenario. Our results show that sensing window estimated incorrect 14 times as large estimation algorithm.

We propose a speculative divide-and-conquer (SDnC) method that enables optimization of large analog/mixed-signal (AMS) circuit. Because modules AMS circuits strongly interact with neighbor modules, they cannot be optimized individually. Therefore, design parameters all must co-optimized for the global optimization, and thus, space exponentially grows circuit size. Although metaheuristic algorithms can enhance efficiency, handle very due to increased size explore. The proposed utilized (DnC)...

This paper presents simple and intuitive closed-form formulas for tradeoff among channel loss, length, frequency of single-ended interconnects to aid fast equalized link estimation. Based on a transfer function model interconnects, we derived two RC- LC-dominant interconnects. The formulas' accuracies computation time improvements are verified by comparison with the SPICE simulation measurement results. According our formulas, loss is roughly linear product length square root in RC-dominant...

In this paper, we propose a search algorithm to find the worst operation scenario of cross-point array phase-change random access memory enable precise read margin evaluation. The utilizes particle swarm optimization method quickly and efficiently. an experiment, proposed improves speed by 39.3× compared with previous algorithm. With improved speed, could scenarios large arrays whose had been only guessed before. experiment array, proved that high-resistance state current can be 36× larger...

In this work, we report the synthesis and photovoltaic properties of IEBICO-4F, IEHICO-4F, IOICO-4F, IDICO-4F non-fullerene acceptors (NFAs) bearing different types alkyl chains (2-ehtylhexyl (EH), 2-ethylbutyl (EB), n-octyl (O), n-decyl (D), respectively). These NFAs are based on central indacenodithiophene (IDT) donor core same terminal group 2-(5,6-difluoro-3-oxo-2,3-dihydro-1H-inden-1-ylidene)malononitrile (IC-2F), albeit with side appended to thiophene bridge unit. Although induced...

This paper presents a body-channel communication (BCC) transceiver adopted with decision feedback equalization (DFE). The proposed transceiver, fabricated in 65-nm CMOS process, achieves reliable (BER<10−6) data rates of 150 Mb/s (16.6 pJ/b), and 100 (23.5 pJ/b) over 20-cm 1.3-m channels on human limbs. occupies total core area 5580 qm2, which is less than 1% compared to any previously-presented work.

In this paper, we propose a code inversion encoding technique to improve the read margin of cross-point phase change memory (PCM). The proposed reduces maximum number low resistance state cells which significantly reduce by increasing sneak current. Therefore, scheme can PCM. To verify improvement technique, simulated and compared margins various arrays with without technique. According simulation, our improves 102% or equivalently allows increase array size 91.6% decreasing for margin....

This paper presents a rule-of-thumb condition on the size of an ReRAM crossbar array to avoid large HRS current in read operation. Although must be small for margin, worst can too significantly reducing margin if is large. According our analysis, starts steeply increasing as increases beyond certain limit. We derived approximate limit terms design parameters current. The formula verified with SPICE simulation demonstrating that engineers nicely estimate maximum without causing

This paper presents a body-channel communication (BCC) transceiver adopted with decision feedback equalization (DFE). The proposed transceiver, fabricated in 65-nm CMOS process, achieves reliable (BER<;10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> ) data rates of 150 Mb/s (16.6 pJ/b), and 100 (23.5 pJ/b) over 20-cm 1.3-m channels on human limbs. occupies total core area 5580 qm xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ,...

Bipolar plate and current collector are important stainless steel components of the molten carbonate fuel cell (MCFC) because they supply pathway electron flow between each unit cell. However, these prone to corrosion in hot environment products forming on surface increase ohmic resistance. In addition, reduces mechanical strength collector, accelerates electrolyte loss, finally leads degradation performance. Therefore, is one main problems MCFC systems. To solve problems, various methods...

We review the speculative divide-and-conquer (SDnC) optimization method. SDnC method is a highly effective for large analog/mixed-signal (AMS) circuits. As size of circuits grows, previous methods face difficulties due to an exponential increase in design complexity. To reduce complexity, decreases evaluation and levels from AMS circuit smaller module units. This significant reduction complexity could be validated through comparisons with other methods, such as parameter sweep PSO....

We present a fast eye size evaluation method for high speed signal. In order to estimate the smallest quickly, worst data pattern, which maximizes inter-symbol interference (ISI) accumulation, is determined by utilizing pulse response and simulated. The proposed compared with SPICE simulation that utilizes pseudo random bit sequence (PRBS) as an input