A temperature-stabilized 12-bit single-channel successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC) running at 1 GS/s with Nyquist signal to noise and distortion ratio (SNDR) above 60 dB is presented. The ADC uses a three-stage (4 b-4 b-6 b) SAR-assisted pipeline hybrid architecture achieve an attractive energy efficiency along extended sampling rate. high-linearity open-loop Gm-R-based residue amplifier (RA) both complete-settled dynamic features...

This article presents a low power-supplied 13-bit 20-MS/s time-to-digital converter (TDC)-assisted successive approximation register (SAR) analog-to-digital (ADC). In this hybrid architecture, the voltage-to-time (VTC) and TDC realize an inherent process, voltage, temperature (PVT) robustness by inner tracking, thus inducing no extra power circuit overheads. The voltage-domain time-domain speed-enhanced techniques accelerate first- second-stage ADC conversions under supply, respectively....

An asymmetrical Fabry-Perot interferometric (AFPI) force sensor is fabricated based on a narrowband reflection of low-reflectivity fiber Bragg grating (LR-FBG) and broadband Fresnel the cleaved end. The AFPI includes section microfiber made by tapering it achieves sensitivity 0.221 pm/μN with tapered 40 mm length 6.1 μm waist diameter. Compared similar structure in 125 μm-diameter single mode fiber, greatly enhanced due to its smaller diameter can be optimized for different scales...

This paper presents an energy-efficient 13-bit 10-50 MS/s subranging pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) with power supply scaling. In the presented ADC, SAR-assisted floating capacitive DAC switching algorithm reduces energy along enhanced linearity and speed in first-stage SAR ADC. A following temperature-insensitive time-based residue amplifier realizes open-loop residual amplification without background calibration, while maintaining...

This paper presents low-power circuit techniques for comparators and controllers to reduce increasing power loss of an active diode with offset/delay calibration in a 13.56-MHz CMOS rectifier. Unlike conventional switched-offset comparator, the proposed voltage-mode comparator reuses its bias current generate continuously adjustable offset voltage, thereby reducing loss. Offset accurate switching is adopted improve conversion efficiency (PCE) voltage ratio (VCR). The switch controller uses...

Continuous technology scaling has allowed unceasing growth of the sampling rate a single channel ADC in past decades. Such development not only helps reduce number channels massively time interleaved ADCs, but also contributes to lower their overall jitter and input capacitance, thus enabling further push on performance boundary. Being limited by metastability, conventional SAR architecture is suitable when both high resolution speed are essential. While pipeline offers higher alternative,...

This article presents an 8-bit time-domain analog-to-digital converter (ADC) that achieves 10 GS/s by aggregating only four time-interleaved channels. It also experiences less than 3.0-dB signal-to-noise and distortion ratio (SNDR) drop at 18-GHz input frequency from a dc due to its small capacitance inherent voltage-to-time (VTC)based sub-channel buffer. A 16× time-interpolation-based timeto-digital (TDC) resolves in two steps while allowing both the inter-stage gain quantization step be...

High-speed pipelined ADCs rely on fast and accurate residue amplification which often necessitates calibration, thus suffering from potential convergence issues, extra area/power overhead, higher test costs. The state-of-the-art open-loop (OL) amplifiers (RAs) accommodate short time [1] with decent calibration-free gain variation over PVT [2], reaching performance is challenging due to the absence of closed loop (CL) assistance. A ring-amp in a CL topology promising alternative, showing <tex...

Direct RF sampling relieves the analog front-end design and delivers high system flexibility. In $\gt10 \mathrm{GS} / \mathrm{s}\gt10 \mathrm{~b}$ ADCs, time-interleaving (TI) is inescapable [1–3], while number of channels their components should be minimized to achieve low power adequate linearity for a wideband input. Moreover, complexity hardware cost associated with background calibrations TI impairments minimized. However, prior face challenges comprehensive, which either confine...

The two-step SAR ADC is an energy-efficient architecture for high-resolution applications, which faces headroom challenges from the voltage-domain residue amplification under a low power supply. A TDC-assisted [1] uses voltage-to-time converter (VTC) and TDC as back-end to quantize voltage of ADC, attractive supply scenarios by moving domain quantization into time domain. However, encounters several design challenges. For example, it sensitive PVT variations due partial time-domain...

The ever-increasing data traffic in wireline communication systems has led to the demand for high-speed ADCs with a large input BW. Time-interleaved SAR interleaving factor suffer from capacitance [1] and often have limited BW, or otherwise they necessitate power-hungry broadband buffer [2]. Flash [3] not only face same challenge parasitics but also resolutions resulting offset. Recently, time-domain [4], [5] shown promising speeds small due their inherent voltage-to-time converter (VTC) as...

This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in digital-to-analog converter (DAC), while its residue voltage increment neutralized through paired comparators with opposite polarity offsets, thereby relaxing design requirement of amplifier. While one generating...

A high‐gain and high‐speed gain‐boosted dynamic amplifier for pipelined‐successive approximation register ADCs is presented. cross‐coupling cascode topology proposed to boost the gain of a single‐stage amplifier. The achieves voltage 32 under 1.2 V power supply in 130 nm CMOS technology. Sampling at 150 MS/s, consumes total 0.22 mW.

This brief presents a linear charger architecture based on single amplifier for regulation and the charging phase transition from constant-current (CC) to constant-voltage (CV) phase. The proposed unified is stacked differential pairs that share bias current. Its current-steering property removes multiple amplifiers CC-CV transition, achieves high unity-gain loop bandwidth fast regulation. with maximum current of 25 mA fabricated in 0.35μm CMOS process. While biased 20 μA, peak efficiency...

Wide bandwidth (BW) and moderate-resolution ADCs with a sampling rate exceeding 10GS/s play vital role in wireline receivers. Time-interleaved (TI) SAR retain low power but exacerbated input BW limitation massive TI factor. Although such an obstacle can be alleviated by the hierarchical sampler [1], remaining long routings [2] among bulky channels jeopardize efficiency linearity. Alternatively, time-domain (TD) ADC [3] reduces channel number achieving superior BW; it however desires much...