A5103236320- Interconnection Networks and Systems
- Parallel Computing and Optimization Techniques
- Embedded Systems Design Techniques
- Low-power high-performance VLSI design
- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Semiconductor materials and devices
- Advanced Memory and Neural Computing
- VLSI and FPGA Design Techniques
- Advanced Wireless Communication Techniques
- Video Coding and Compression Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Wireless Communication Networks Research
- Advanced Vision and Imaging
- Advanced Data Compression Techniques
- Error Correcting Code Techniques
- Pituitary Gland Disorders and Treatments
- Embedded Systems and FPGA Design
- Ferroelectric and Negative Capacitance Devices
- PAPR reduction in OFDM
- Analog and Mixed-Signal Circuit Design
- Advancements in PLL and VCO Technologies
- 3D IC and TSV technologies
- Advanced Data Storage Technologies
- Advanced Neural Network Applications
Shanghai Jiao Tong University
2016-2025
Sichuan University
2025
West China Hospital of Sichuan University
2025
Sun Yat-sen University
2010-2024
Shanghai Ninth People's Hospital
2024
Harbin Institute of Technology
2013-2022
The First Affiliated Hospital, Sun Yat-sen University
2021
University of International Business and Economics
2020
Heilongjiang Institute of Technology
2005-2019
Massachusetts General Hospital
2016
In this paper, a novel low-power and highly reliable radiation hardened memory cell (RHM-12T) using 12 transistors is proposed to provide enough immunity against single event upset in TSMC 65 nm CMOS technology. The obtained results show that the can not only tolerate at its any sensitive node regardless of polarity strength, but also recover from multiple-node induced by charge sharing on fixed nodes independent stored value. Moreover, has comparable or lower overheads terms static power,...
In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed Cadence Spectre demonstrate ability radiation-hardened-by-design tolerate both 0 → 1 single node upsets,...
Abstract Background The purpose of this study was to (1) identify specific miRNAs in growth hormones (GH)-secreting pituitary adenomas; (2) determine the relationship between expression these and tumor size, somatostatin analogs treatment, responsiveness (SSA). Methods Fifteen GH-secreting adenomas patients were treated with lanreotide for 4 months before surgery. Patients 50% reduction GH secretion by considered as SSA responders, while less than nonresponders. We analyzed 21 6 normal...
In this paper, a novel radiation-hardened-by-design (RHBD) 12T memory cell is proposed to tolerate single node upset and multiple-node based on physical mechanism behind soft errors together with reasonable layout-topology. The verification results obtained confirm that the can provide good radiation robustness. Compared 13T cell, increased area, power, read/write access time overheads of are -18.9%, -23.8%, 171.6%/-50.0%, respectively. Moreover, its hold static noise margin 986.2 mV which...
The heavily-threaded data processing demands of streaming multiprocessors (SM) in a GPGPU require large register file (RF). fast increasing size the RF makes area cost and power consumption unaffordable for traditional SRAM designs future technologies. In this paper, we propose to use embedded-DRAM (eDRAM) as an alternative GPGPUs. Compared with SRAM, eDRAM provides higher density lower leakage power. However, limited retention time poses new challenges. Periodic refresh operations are...
Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) widely used protect memory, but main problem is that they would require higher delay overhead. Recently, matrix (MCs) based on Hamming have been proposed for memory protection. The issue double and capabilities not improved all cases. In this paper, novel decimal code (DMC)...
Superwetting surfaces are widely used in many engineering fields for reducing energy and resistance loss. A facile efficient method using laser etching has been to fabricate control superwettable drag reduction surfaces. Inspired by the self-cleaning theory of lotus leaves, we propose controllable patterned bionic superhydrophobic (BSSs) simulating uneven micro/nanostructures leaves. The superhydrophobicity ratios at low velocities highly improved a ablation on metal substrates. However,...
Radiation-induced single event upsets (SEUs), or soft errors, have become a dominant factor in the reliability degradation of nanoscale memories. In this paper, based on SEU physics mechanism, and reasonable layout-topology, novel error hardened memory cell is proposed 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The design comparisons for several cells terms access time (read write time), power consumption, layout area are also executed. main advantage that it can...
Abstract Diabetes, a highly prevalent disease that affects 9.3% of Americans, often leads to severe complications and slow wound healing. Preclinical studies have suggested low level light therapy (LLLT) can accelerate healing in diabetic subjects, but significant improvements must be made overcome the absence persuasive evidence for its clinical use. We demonstrate here LLLT combined with topical Coenzyme Q10 (CoQ10) heal wounds mice significantly faster than alone, CoQ10 or controls....
Inspired by the bionic fish scale surfaces containing micro/nanostructured arrays, herein, applications of lubricant‐impregnated anisotropic slippery (LIASSs) using laser ablation aluminum–magnesium alloys are proposed. Different hydrophobic properties presented on LIASSs along parallel direction and reverse defined as directions A B micro/nanostructures. self‐assembled solid–liquid interface friction test device is set up to demonstrate drag reduction property LIASSs. The ratios found be...
Logic-in-memory with memristive crossbars is an attractive approach for realizing beyond von Neumann architectures. Multi-valued logic (MVL) containing more than two levels can enhance the computing speed reduced number of operations. In this paper, a binary-compatible multi-valued logic-in-memory (BC-MVLiM) scheme proposed dual-crossbars where both inputs and outputs are represented by multi-level cells memristors. Both binary multiple-valued operations be implemented in BC-MVLiM depending...
Abstract Background Screening of malignant hematological diseases is great importance for their diagnosis and subsequent treatment. This study constructed an optimal screening model based on routine blood cell parameters. Methods The venous samples 1751 patients collected from 10 tertiary hospitals in China were divided into a training set (1223 cases) validation (528 cases). In addition to the clinical diagnostic information set, 26 parameters including morphological selected using manual...
This paper presents a multi-objective exploration approach to map the IP cores onto Network on Chip (NoC). The NoC mapping problem is treated as two conflicting objective optimization of minimizing average hop and achieving thermal balance. Thus set Pareto-optimal mapping, instead single an efficient solution. proposed uses novel representation genetic algorithm capable finding multiple solutions simultaneously for different performance requirement. Experimental results show highly accurate.
Automatic ship detection in optical remote-sensing (ORS) images has wide applications civil and military fields. Research on ORS started late compared to synthetic aperture radar (SAR) images, it is difficult for traditional image-processing algorithms achieve high accuracy. Therefore, we propose a ship-detection method based deep convolutional neural network that modified from YOLOv3. We call fused features rebuilt (FFR) tried some improvements enhance its performance regions. added...
Coarse-Grained Reconfigurable Architectures (CGRA) is a promising solution for accelerating computation intensive tasks due to its good trade-off in energy efficiency and flexibility. One of the challenging research topic how effectively deploy loops onto CGRAs within acceptable compilation time. Modulo scheduling (MS) has shown be efficient on deploying CGRAs. Existing CGRA MS algorithms still suffer from challenge mapping loop with higher performance under time, especially large irregular...
Deep learning accelerators have emerged to enable energy-efficient and high-throughput inference from edge devices such as self-driving cars smartphones, data centers for batch recommendation systems. However, the actual energy efficiency throughput of a deep accelerator depends on neural network (DNN) loop nest mapping processing element array an accelerator. Moreover, dramatically changes by target DNN layer dimensions available hardware resources. Therefore, optimal search problem is...