Abstract In this paper, an LC-VCO architecture incorporating a novel tunable active inductor using 90 nm gpdk technology for wireless communication systems is proposed. The presented here employs three-stage cascoding strategy, with transistors operating in the subthreshold region. proposed topology of then implemented place conventional resonant circuits to increase tuning range. simulation results exhibit high Q-factor 3040 at 8.1 GHz and low inductance 2.26 nH. generates frequency range...

An improved design of four-stage CMOS differential ring voltage-controlled oscillator (VCO) with high-output frequency, low phase noise, and power consumption is proposed in this paper. A new delay cell has been used for VCO which utilises dual-delay-path topology to attain both frequency noise. The simulation results have obtained TSMC 0.18-µm process a supply voltage (Vdd) 1.8 V. exhibits an output oscillation range from 1.619 3.712 GHz. varies 4.628 10.545 mW control variation 0.1 1.0...

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272µW in 0.35µm technology with supply voltage 3.3V.Minimum level for high output 2.05V and maximum low 0.084V have obtained.A single bit full adder eight designed proposed cell, 581.542µW.Minimum 1.97V 0.24V is obtained sum signal.For carry signal 0.32V minimum 3.2V achieved.Simulations performed by SPICE based on TSMC CMOS technology.Power consumption compared earlier reported...

With scaling of Vt sub-threshold leakage power is increasing and expected to become significant part total consumption.In present work three new configurations level shifters for low application in 0.35µm technology have been presented.The proposed circuits utilize the merits stacking technique with smaller current reduction power.Conventional shifter has improved by addition NMOS transistors, which shows consumption 402.2264pW as compared 0.49833nW existing circuit.Single supply modified...

The research presents a modern way of bi-wheels differential mode odometry to predict the next planar and angular co-ordinate mobile robots. presented incorporates two independent wheels with respective encoders. rotation is independent, change determined by difference in velocity bi-wheels. Rotational velocities are A Mathematical model proposed for robots precisely move towards goal. Using calculated data encoders, present displacement robot measured model. With help displacement,...

The performance of voltage controlled oscillator (VCO) is great importance for any telecommunication or data transmission network. Here, oscillators (VCOs) using three-transistor NAND gates have been designed. New delay cell with gate has used designing the ring based VCO circuits. Three-, five-, and seven-stage VCOs proposed. Output frequency supply variation from 1.8 V to 2.4 V. Three stage shows output in range 3.2909 GHz 4.2280 whereas power consumption varies 335.4071 μ W 486.1816 W....

A digitally controlled oscillator (DCO) using a three-transistor XOR gate as the variable load has been presented. delay cell an inverter and capacitance is also proposed. Three-, five- seven-stage DCO circuits have designed proposed cell. The output frequency with bits applied to cells. three-bit shows power consumption variation in range of 3.2486–4.0267 GHz 0.6121–0.3901 mW, respectively, change control word 111–000. five-bit achieves 1.8553–2.3506 1.0202–0.6501 11111–00000. Moreover,...

In this paper, a low-power high speed 4-2 compressor circuit is proposed for fast digital arithmetic integrated circuits. The has been widely employed multiplier realizations. Based on new exclusive OR (XOR) and NOR (XNOR) module, designed. Proposed shows power consumption variation in the range of 718.72 pW to 3357.40 pW. Maximum output delay presents 43.83 ps 27.74 ps. Further, power-delay product (PDP) varying from 315.01×10-22(J) 931.34×10-22(J) with change supply voltage 1.8V 3.3V....

This paper presents the ADPLL design using Verilog and its implementation on FPGA. is designed HDL. Xilinx ISE 10.1 Simulator used for simulating Code. gives details of basic blocks an ADPLL. In this paper, described in detail. Its simulation results are also discussed. It FPGA vertex5 xc5vlx110t chip results. The 200 kHz central frequency. operational frequency range 189 Hz to 215 kHz, which lock design.

This paper reports a new design of low power two bit magnitude comparator with adiabatic logic in 0.18µm CMOS technology. The proposed shows the improvement delay product (PDP) 66.76% to 82.97% varying supply for 1.1V 2.0V as compared conventional design. PDP an 73.98% 81.15 % temperature from 50°C 10°C Results show significant terms existing designs.

This paper proposes the implementation of an ancient Indian Vedic multiplier using 16 bit modified carry select adder, ripple adder and kogge stone adder. The shows improved speed performance with less time delay. design has been implemented Verilog hardware description language. code is tested Modelsim simulator. synthesized Virtex-7 family. family based on 28nm which 50 percent lower power compared to previous generation Virtex-6. makes a comparison three different adders Results that...

This manuscript postulates two new designs of dual-delay stage for the four-stage CMOS differential ring voltage controlled oscillators (VCOs). Ring VCOs use path techniques to achieve a wide tuning range with low power dissipation. The proposed are designed in TSMC 0.13 ​μm technology supply 1.3 ​V. VCO-1 generates ranges from 5.188 7.932 ​GHz (41.82%), whereas its dissipation varies 1.853 2.711 ​mW by change control −1.0 ​V 0 VCO-2 based on I-MOS varactors produces 4.918 7.268 (38.56%) and...

Voltage controlled oscillator (VCO) is widely used circuit component in high-performance microprocessors and modern communication systems as a frequency source. In present work, VCO designs using the different combination of NAND gates with three transistors CMOS inverter are reported. Three, five seven stages ring circuits designed. Coarse fine tuning have been done two supply sources. The coarse varies from 3.31 GHz to 5.60 stages, 1.77 3.26 1.27 2.32 respectively. Moreover, for 3.70 3.94...

This paper presents a new design of low power voltage controlled oscillator (VCO) circuit using three transistors NOR-gate and I-MOS (inversion mode) varactor tuning method. Variation in the oscillation frequency has been obtained by varying output load capacitance with use consisting two PMOS connected parallel. Variable across achieved source/drain ([Formula: see text] back-gate text]. [Formula: from 1[Formula: text]V to 2[Formula: provides deviation 1.970[Formula: text]GHz 1.379[Formula:...