A5101600110- Electronic Packaging and Soldering Technologies
- 3D IC and TSV technologies
- Nanofabrication and Lithography Techniques
- Economic and Environmental Valuation
- Microbial Inactivation Methods
- Conservation, Biodiversity, and Resource Management
- Genetics and Neurodevelopmental Disorders
- Inflammatory Bowel Disease
- Land Use and Ecosystem Services
- Chromosomal and Genetic Variations
- Anomaly Detection Techniques and Applications
- Fungal and yeast genetics research
- Synthesis and properties of polymers
- bioluminescence and chemiluminescence research
- Semiconductor materials and interfaces
- Auction Theory and Applications
- Genomic variations and chromosomal abnormalities
- RNA and protein synthesis mechanisms
- Domain Adaptation and Few-Shot Learning
- Advanced Welding Techniques Analysis
- Digital Platforms and Economics
- Prenatal Screening and Diagnostics
- Eosinophilic Esophagitis
- Metal and Thin Film Mechanics
- Game Theory and Applications
Tsinghua University
2012-2024
Capital Institute of Pediatrics
2024
Institute of Microelectronics
2012-2016
INTRODUCTION It has long been an interesting question whether a living cell can be constructed from scratch in the lab, goal that may not realized anytime soon. Nonetheless, with advances DNA synthesis technology, complete genetic material of organism now synthesized chemically. Hitherto, genomes several organisms including viruses, phages, and bacteria have designed constructed. These synthetic are able to direct all normal biological functions, capable self-replication production...
Currently, biodiversity conservation and the achievement of common prosperity are important challenges. China bid farewell to “absolute poverty” in 2020 but continues face challenges, such as relative multidimensional poverty, especially regions protected areas (PA). The correlation between poverty natural environment leads further research on distribution spatiotemporal evolutionary characteristics affected by restrictive policies PA. Quantitative these helps researchers formalize...
Wafer bumping is a key process for flip chip packaging. There are several techniques such as ball drop, electroplating and stencil printing, in which printing thought to be an economical choice because it compatible with conventional SMT technology. However, when bump pitch less than 100 μm, becomes more difficult control the deposition volume of solder paste. In this paper, multiple parameters had been characterized by orthogonal experiment method find optimal setting 4" wafer 90μm pitch....
MIS (Molded Interconnect System) substrate, as a type of coreless has the advantages lower profile and higher electrical performance. However, warpage would be one major concern without mechanical support core material. In this study, multilayered substrate been simulated using finite element analysis (FEA). Coefficients thermal expansion (CTE) elastic modulus constituent materials had measured. To properly simplify composite structure, orthotropic equivalent material parameters have...
As a low cost solution to realize fine line structure for high density chip interconnection, the thin film organic substrate that adopted same concept as flip RDL (redistribution layers) technology has been developed in this study. The coarse of conventional could be refined much finer distribution through application process. layers had deposited on both sides 4-inch diameter BT by Cu sputtering and electroplating. dielectric material, was built-up spin coating Daisy chain testing circuit...
Wafer bumping is a key process for flip chip packaging. There are several techniques such as ball drop, electroplating and stencil printing, in which printing thought to be an economical choice because it compatible with conventional SMT technology. However, when bump pitch less than 100 μm, becomes more difficult control the deposition volume of solder paste. In this paper, multiple parameters had been characterized by orthogonal experiment method find optimal setting 4” wafer 90μm pitch....
Silicon interposer with Through Via (TSV) has been a promising technology for 3D integration. Good thermal property is one of the advantages. Thermal resistance was usually used to estimate package. In order obtain silicon interposer, chip junction temperature needs be measured. However, it challenge acquire T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">j</sub> because hotspot in difficult detected. this work, test containing diodes employed...