A5101619835- Particle Detector Development and Performance
- Advancements in PLL and VCO Technologies
- Radiation Detection and Scintillator Technologies
- Semiconductor materials and devices
- Radiation Effects in Electronics
- Advancements in Semiconductor Devices and Circuit Design
- CCD and CMOS Imaging Sensors
- Semiconductor Lasers and Optical Devices
- Photonic and Optical Devices
- Particle physics theoretical and experimental studies
- VLSI and Analog Circuit Testing
- Sulfur-Based Synthesis Techniques
- Radio Frequency Integrated Circuit Design
- Semiconductor Quantum Structures and Devices
- Organoselenium and organotellurium chemistry
- Integrated Circuits and Semiconductor Failure Analysis
- Analog and Mixed-Signal Circuit Design
- Catalytic Cross-Coupling Reactions
- Ferroelectric and Negative Capacitance Devices
- Low-power high-performance VLSI design
- Chemical Synthesis and Reactions
- Catalytic C–H Functionalization Methods
- Synthetic Organic Chemistry Methods
- Advanced Optical Sensing Technologies
- Wireless Sensor Networks and IoT
Anhui University of Technology
2025
University of California, Santa Barbara
2023-2024
Nanning Normal University
2024
Southern Methodist University
2020-2024
Central China Normal University
2017-2024
University of South China
2024
National Yang Ming Chiao Tung University
2024
Institute of High Energy Physics
2023
European Organization for Nuclear Research
2023
University of Chinese Academy of Sciences
2023
The selective laser ablation of pancreatic ductal adenocarcinoma (PDAC) which is an aggressive and highly lethal solid tumor great significance. However, existing thermal methods such as radiofrequency, microwave all lack the ability to selectively ablate cancerous tissue while preserving healthy pancreas. In this study, by developing a 6.1 μm femtosecond at resonant wavelength collagen with output power exceeding 1 W, we demonstrate PDACs from 13 patients significant preservation normal...
The selective laser ablation of pancreatic ductal adenocarcinoma (PDAC) which is an aggressive and highly lethal solid tumor great significance. However, existing thermal methods such as radiofrequency, microwave all lack the ability to selectively ablate cancerous tissue while preserving healthy pancreas. In this study, by developing a 6.1 μm femtosecond at resonant wavelength collagen with output power exceeding 1 W, we demonstrate PDACs from 13 patients significant preservation normal...
In this letter, we report for the first time degradation mechanism of drain current in tunneling field-effect transistors (TFETs). Using positive-bias and hot-carrier (HC) stress experiments TCAD simulation, show that is mainly induced by interface traps and/or oxide charge located above region, causing reduction field current. The induce transconductance, while essentially causes a threshold-voltage shift TFETs. results interface-trap generation dominant under stress, oxide-charge creation...
Tunneling n-FET reliability performance is studied for the first time by physical analysis and experimental measurements. (1) A new degradation mechanism interface trap induced change of tunneling field current I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> demonstrated. (2) Under PBTI or HC stress, there a strong peak vertical electric E xmlns:xlink="http://www.w3.org/1999/xlink">x</inf> at gate/source overlapping region due to P...
We present the design and test results of a Time-to-Digital-Converter (TDC). The TDC will be part readout ASIC, called ETROC, to read out Low-Gain Avalanche Detectors (LGADs) for CMS Endcap Timing Layer (ETL) High-Luminosity LHC upgrade. One challenges ETROC is that required consume less than 200 W each pixel at nominal hit occupancy 1%. To meet low-power requirement, we use single delay line both Time Arrival (TOA) over Threshold (TOT) measurements without control. A double-strobe...
A configurable-bandwidth charge-domain filter (CDF) with bandwidth calibration and clock-pulse modulation (CPM) is proposed. The scheme controls the insertion loss at a pre-specified frequency by modulating feedback gain delay; this helps CDF to suppress sinc distortion thus achieve near-ideal brick-wall filtering. For multi-frequency compensation, multi-stage architecture utilized organize delay. Together non-decimation filtering, noise folding effect as well chip area can be reduced. On...
Abstract A very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When small charge injected into circuit, it flips rapidly due to outputs logic transition further digitization. Simulation shows that 65 nm process, possible achieve detecting threshold below 5 fC while maintain average consumption 10...
High-k metal oxides are gradually replacing the traditional SiO2 dielectric layer in new generation of electronic devices. In this paper, we report production five-element high entropy (HEMOs) films by solution method and analyzed role each oxide system characterizing film properties. On basis, found optimal combination (AlGaTiYZr)Ox with best properties, exhibiting a low leakage current 1.2 × 10−8 A/cm2 @1 MV/cm constant, while film’s visible transmittance is more than 90%. Based on results...
We report, for the first time, reliability issues of tunneling field-effect transistors (TFETs) by experiments. observed that overall performance n-TFETs is very different from those conventional n-MOSFET. The degradation under positive bias temperature instability (PBTI) stress large compared with negligible hot-carrier also larger than in n-MOSFET and has a dependence. shifts <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub...
We demonstrate simultaneous NMOS and PMOS high-field mobility enhancement variability reduction by inserting partial monolayers of oxygen during silicon epitaxy the channel layer.
We present a low-noise Charge-Sensitive Amplifier (CSA) manufactured in standard 0.35 μm CMOS process. The CSA is part of an integrated sensor named Topmetal-S, array which forms charge readout plane high-pressure gaseous TPC for 0νββ search. A single-ended folded cascode amplifier with 73 dB open-loop gain and 340 MHz gain-bandwidth product the main amplification stage this CSA. Measurements show that conversion 3 fF feedback capacitor 163 mV/fC. With 5 pF detector capacitance, achieved...
Abstract The time-to-digital-converter (TDC) using uncontrolled delay lines has a simple structure and finer measurement precision since the cells are pure digital gates that operate at maximum speed. For every incoming hit, two “snapshots” of line taken by register array with strobes separated known time interval. With measurements, propagation delays each cell in can be calibrated for operating temperature voltage. measurements also averaged to improve TDC precision. We will discuss...
Abstract This paper presents the design and test results of a Gigabit Cable Receiver ASIC called GBCR for HL-LHC upgrade ATLAS Inner Tracker (ITk) pixel detector. Three prototypes (GBCR1, GBCR2, GBCR3) have been designed in CERN-identified 65 nm CMOS technology. receives seven (GBCR2) or six (GBCR3) channels (RX) each at 1.28 Gbps from front-end readout chip RD53B via flex cables up to 1 meter Twinax 5 meters sends equalized retimed signals lpGBT. Both GBCR2 GBCR3 ASICs two transmitting (TX)...
This paper presents the design and simulation results of a gigabit transceiver Application Specific Integrated Circuit (ASIC) called GBCR for ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. has four upstream receiver channels downstream transmitter channel. Each channel operates at 5.12 Gbps, while 2.56 Gbps. In each channel, equalizes signal received through 5-meter 34-American Wire Gauge (AWG) twin-axial cable, retimes data with recovered clock, drives an optical transmitter....
The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in CMS Endcap Timing Layer (ETL) has been prototyped a 65 nm CMOS mini-ASIC named ETROC0. Serving as very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate performance frontend, with goal achieve 40 50 ps time resolution per hit LGAD (therefore reach about 30ps track two detector-layer hits track). consists preamplifier discriminator stages, which amplifies...
It is widely recognized that recovery during measurement delay seriously misleads the BTI phenomena. We have developed a modified Charge Pumping (MCP) method to measure interface trap generation under stress with negligible delay. The simply extends inversion level Vinv of CP pulse voltage and keeps duty cycle as large possible, therefore almost "on" measurement. For first time, we diagram representation process used physical analysis for contribution exclusion slow oxide charge in current...
This paper presents a low-cost pre- and post-bond self-testing calibration methodology for the successive approximation register (SAR) analog-to-digital converter (ADC) array in three-dimensional (3-D) CMOS imager. The basic idea is to test calibrate SAR ADC by measuring major carrier transitions (MCTs) of internal digital-to-analog (DAC) capacitor array. During pre-bond stage, when access die very limited, we propose calibration-oriented testing technique that only determines whether can...
Abstract We present the design and performance of MUX64, a 64-to-1 analogue multiplexer ASIC for ATLAS High Granularity Timing Detector (HGTD). The MUX64 transmits one its 64 inputs selected by six address lines voltages or temperatures being monitored to an lpGBT ADC channel. prototype ASICs fabricated in TSMC 130 nm CMOS technology were prepared wire-bonding QFN88 packaging format. A total 280 chips was examined functionality quality assurance. accelerated aging test conducted at 85 °C...
The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices. This paper discusses process impact on LER/LWR, well 2D LER performance variation and degradation. And it found that SNWTs, which immune to channel RDF(random dopant fluctuation), exhibit SDE-RDF enhanced by diameter-dependent annealing. In addition, different impacts experimentally extracted sources in SNWTs threshold voltage current flucturation...