A5068991400- Security and Verification in Computing
- Formal Methods in Verification
- Physical Unclonable Functions (PUFs) and Hardware Security
- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- Logic, programming, and type systems
- Advanced Malware Detection Techniques
- Vehicular Ad Hoc Networks (VANETs)
- Thermodynamic properties of mixtures
- Integrated Circuits and Semiconductor Failure Analysis
- Autonomous Vehicle Technology and Safety
- Parallel Computing and Optimization Techniques
- Software Testing and Debugging Techniques
- Adversarial Robustness in Machine Learning
- Safety Systems Engineering in Autonomy
- Logic, Reasoning, and Knowledge
- IoT and Edge/Fog Computing
- Network Security and Intrusion Detection
- Advanced Memory and Neural Computing
- Anomaly Detection Techniques and Applications
- Distributed systems and fault tolerance
- Advanced Neural Network Applications
- Chemical and Physical Properties in Aqueous Solutions
- Semiconductor materials and devices
University of Florida
2014-2025
Marvell (United States)
2025
Lady Hardinge Medical College
2016-2022
The University of Texas at Dallas
2022
Kalawati Saran Children's Hospital
2016-2021
ESIC Hospital
2021
Creative Commons
2021
The University of Texas at Austin
2005-2018
Intel (United Kingdom)
2014-2018
University of California, Santa Barbara
2018
This Tutorial paper is about the Internet of Things, its applications, challenges, and how it may change way computing. Besides a comprehensive introduction, focuses on two major design constraints, namely, security power management.
This paper provides a tutorial overview of the state-of-the-art in verification complex and heterogeneous Systems-on-Chip. The authors discuss current industrial trends key research challenges.
Modern system-on-chip (SoC) designs include a wide variety of highly sensitive assets which must be protected from unauthorized access. A significant aspect SoC design involves exploration, analysis, and evaluation resiliency mechanisms against attacks to such assets. These may arise number sources, including malicious intellectualproperty blocks (IPs) in the hardware, or vulnerable firmware software, insecure communication system with other devices, side-channel vulnerabilities through...
Editor's note: Post-silicon validation is a complex and critical component of modern system-on-chip (SoC) design verification. It includes large number inter-related activities each with its own nuance subtleties, requires extensive planning, spans the entire system lifecycle. This article provides comprehensive high-level overview various facets post-silicon validation, industrial case studies illustrating their real-life application.
Cooperative Adaptive Cruise Control (CACC) is a fundamental connected vehicle application that extends by exploiting vehicle-to-vehicle (V2V) communication. CACC crucial ingredient for numerous autonomous functionalities including platooning, distributed route management, etc. Unfortunately, malicious V2V communications can subvert CACC, leading to string instability and road accidents. In this paper, we develop novel resiliency infrastructure, RACCON, detecting mitigating attacks on CACC....
Modern system-on-chip (SoC) designs involve integration of a large number intellectual property (IP) blocks, many which are acquired from untrusted third-party vendors. An IP containing security vulnerability-whether inadvertent or malicious-may compromise the trustworthiness entire SoC, e.g., by leaking sensitive information causing execution failures at key points. Existing functional validation approaches, post-manufacturing tests, and trust verification techniques inadequate to...
Modern SoC designs incorporate several security policies to protect sensitive assets from unauthorized access. The affect multiple design blocks, and may involve subtle interactions between hardware, firmware, software. This makes it difficult for designers implement these policies, system validators ensure adherence. Associated problems include complexity in upgrading IP reuse systems targeted markets with differing requirement, consequent increase time time-to-market. In this paper, we...
A key problem in post-silicon validation is to identify a small set of traceable signals that are effective for debug during silicon execution. Most signal selection techniques rely on metric based circuit structure. Simulation-based promising but have major drawbacks computation overhead and restoration quality. In this paper, we propose an efficient simulation-based technique address these bottlenecks. Our approach uses (1) bounded mock simulations determine state effectiveness, (2)...
This article surveys recent advances in hybrid approaches for functional verification. These combine multiple verification techniques so that they complement one another, resulting superior effectiveness.
Systematic implementation of System-on-Chip (SoC) security policies typically involves smart wrappers extracting local critical events interest from Intellectual Property (IP) blocks, together with a control engine that communicates the to analyze for policy adherence. However, developing customized at each IP requirements may incur significant overhead in area and hardware resources. In this paper, we address problem by exploiting extensive design-for-debug (DfD) instrumentation already...
We consider the conflicts between requirements from security and post-silicon validation in SoC designs. Post-silicon requires hardware instrumentations to provide observability controllability during on-field execution; this turn makes system prone vulnerabilities, resulting potentially subtle exploits. Mitigating such threats while ensuring that is amenable challenging, involving close collaboration among security, validation, testing, computer architecture teams. examine state of practice...
Modern SoC designs incorporate several security policies to protect sensitive assets from unauthorized access. The affect multiple design blocks, and may involve subtle interactions between hardware, firmware, software. This makes it difficult for designers implement these policies, system validators ensure adherence. Associated problems include complexity in upgrading IP reuse systems targeted markets with differing requirement, consequent increase time time-to-market. In this paper, we...
State Restoration Ratio (SRR) has been the de facto standard for evaluating quality of signals selected post-silicon tracing and debug. Given a set S signals, SRR measures fraction (gate-level) design states that can be inferred from observing in at each cycle. Unfortunately, spite its widespread use, we found is intrinsically unsuitable as metric trace signal quality, it captures neither higher-level functionality nor constraints requirements on imposed by architectural, physical, or...
A key problem in postsilicon validation is to identify a small set of traceable signals that are effective for debug during silicon execution. Structural analysis used by traditional signal selection techniques leads poor restoration quality. In contrast, simulation-based provide superior restorability but incur significant computation overhead. this paper, we propose an efficient technique using machine learning take advantage while significantly reducing the simulation The basic idea train...
Modern technological industries fused with the Internet-of-Things (IoT) have been advancing rapidly. The joint usage of several technologies has led to reshaping modeling and simulation techniques into virtualization physical systems. Thus, concept virtual prototyping emerged as a significant development in distributed IoT applications that includes early exploration, optimization, security assessments. Several employing various types e.g., platforms, digital twins, application-specific...
We describe a method that permits the user of mechanized mathematical logic to write elegant logical definitions while allowing sound and efficient execution. In particular, features supporting this allow install, in logically way, alternative executable counterparts for defined functions. These alternatives are often much more than equivalent terms they replace. have been implemented ACL2 theorem prover, we discuss several applications ACL2.
Although concolic testing is increasingly being explored as a viable software verification technique, its adoption in mainstream development and the industry not yet extensive. In this paper, we discuss challenges to widespread of an industrial setting highlight further opportunities where can find renewed applicability.