A5029908562- Semiconductor materials and devices
- Thin-Film Transistor Technologies
- Advanced Memory and Neural Computing
- X-ray Diffraction in Crystallography
- Crystallization and Solubility Studies
- Ferroelectric and Negative Capacitance Devices
- CCD and CMOS Imaging Sensors
- Advancements in Semiconductor Devices and Circuit Design
- Photonic and Optical Devices
- Electronic and Structural Properties of Oxides
- ZnO doping and properties
- Silicon Nanostructures and Photoluminescence
- Transition Metal Oxide Nanomaterials
- Gas Sensing Nanomaterials and Sensors
- Advanced Optical Imaging Technologies
- Semiconductor Lasers and Optical Devices
- Advanced Semiconductor Detectors and Materials
- Advanced Data Storage Technologies
- Nanocluster Synthesis and Applications
- Ferroelectric and Piezoelectric Materials
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Materials and Mechanics
- Parallel Computing and Optimization Techniques
- Crystallography and molecular interactions
- Silicon Carbide Semiconductor Technologies
Semiconductor Energy Laboratory (Japan)
2014-2024
The University of Tokyo
2023
Emerging nonvolatile memory with an oxide–semiconductor-based thin-film transistor (TFT) using indium-gallium-zinc-oxide (IGZO) was developed. The is called oxide–semiconductor random access (NOSRAM). cell of the NOSRAM (NOSRAM cell) consists IGZO TFT for data writing, a normal Si-based p-channel metal-oxide-semiconductor (PMOS) reading, and capacitor storing charge controlling PMOS gate voltage. are formed over PMOS. Owing to extremely low-leakage-current characteristics TFT, stored in 2-fF...
We have fabricated two monolithic 3D-stacked c- axis aligned crystalline In-Ga-Zn oxide FETs (CAAC-IGZO FETs) with a gate length of 72nm using CAAC-IGZO as the channel material. Estimated off-state leakage current at 85°C, estimated write time for dynamic semiconductor RAM -40°C, nonvolatile and endurance 27°C are less than 5.0 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-20</sup> A/μm, 1.0 to 3.0 ns, 10.0 more...
We fabricated a dynamic random access memory (DRAM) using crystalline oxide semiconductor (OS) transistors and not requiring refresh for more than ten days. call this (DOSRAM). A is an In-Ga-Zn-oxide (IGZO) has c-axis aligned crystal (CAAC) structure. OS transistor extremely low off-state current. The DOSRAM uses device transistors, can have very long cycle. cell array made of layer be stacked on peripheral circuits silicon (Si) layer; thus, the area decreased.
Low-power embedded memory and an ARM Cortex-M0 core that operate at 30 MHz were fabricated in combination with a 60-nm c-axis aligned crystalline indium-gallium-zinc oxide FET 65-nm Si CMOS. The adopted structure which semiconductor-based 1T1C cells are stacked on sense amplifiers. This achieved standby power of 3 nW while retaining data active 11.7 μW/MHz by making each bitline as short amplifier. M0 the flip-flop 3T1C cell is scan without area overhead 6 data. provided high-performance,...
Abstract In 2009, a crystalline oxide semiconductor with layered structure, which we refer to as c ‐axis–aligned indium‐gallium‐zinc ( CAAC ‐ IGZO ), was first discovered. has peculiar crystal structure in clear grain boundaries are not observed despite high ‐axis alignment and absence of b plane alignment. When compared Si field‐effect transistor FET metal‐oxide‐semiconductor MOS ) , utilizing presents lower off‐state current (on the order yA [10 −24 A]). These unique characteristics allow...
We developed an organic light-emitting diode (OLED)/oxide semiconductor (OS)/silicon (Si) display in which Si CMOS drivers can be arranged two-dimensionally by monolithically stacking c-axis-aligned crystalline oxide (CAAC-OS) FETs over CMOS.A CAAC-OS FET exhibits a higher withstand voltage than SiFET of the same size, enabling considerable pixel area reduction.The driven even at low refresh rate owing to its extremely off-state current, making it ideal choice for constructing circuits.This...
We present a three-dimensional (3D) DRAM prototype, which is formed using oxide semiconductor FETs (OSFETs) monolithically stacked on Si CMOS.The OSFETs are composed of one-layer planar FET and two-layer vertical (VFETs).The 1T1C memory cells in the VFET layers primary sense amplifier layer, heterogeneous OSFETs, provide various circuit functions DRAM.The operation 3D 1-Mbit array demonstrated for first time.The results show that proposed operates with read write times 60 ns 50 ns,...
We propose Non-Volatile Oxide Semiconductor Random Access Memory (NOSRAM) that is a novel memory including transistor using an oxide semiconductor, In-Ga-Zn Oxide. OS transistors feature extremely low leakage current of about 100-600 yA/μm (1 yA = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-24</sup> A) at 85°C for example, and are applicable to elements. Our prototype 1Mb NOSRAM has achieved...
We fabricated a 1.50‐inch, 3207‐ppi OLED display with drivers capable of 32‐division driving, which is achieved by monolithically stacking OSFETs over SiFETs. Taking advantages minute high withstand voltage, Si‐OS connection regions were provided in subpixels to connect Si and OS pixel arrays at given positions.
Abstract In order to reduce infection risk of novel coronavirus (SARS-CoV-2), we developed nano-photocatalysts with nanoscale rutile TiO 2 (4–8 nm) and Cu x O (1–2 nm or less). Their extraordinarily small size leads high dispersity good optical transparency, besides large active surface area. Those photocatalysts can be applied white translucent latex paints. Although clusters involved in the paint coating undergo gradual aerobic oxidation dark, oxidized are re-reduced under > 380 light....
A 3bit/cell nonvolatile oxide semiconductor RAM (NOSRAM) test die comprising c-axis aligned crystal In-Ga-Zn-O TFTs has been fabricated. The write time of the is 100 ns. collectively reads multilevel data within 900 ns with a 3bit A/D converter serving as reading circuit. endurance NOSRAM cell more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cycles.
In this paper, we fabricate a 1.50‐inch, 3207‐ppi prototype OLED display with drivers capable of 32‐division driving, which is achieved by monolithically stacking CAAC‐OS FETs over SiFETs. This structure enables narrow bezel and two‐dimensional driver arrangement, leading to independent driving 32 pixel arrays divided source gate lines.
A flip-flop achieving high-speed backup utilizing a Si transistor and long-term retention with zero standby power by means of c-axis aligned crystalline (CAAC) In-Ga-Zn oxide, kind CAAC oxide semiconductor, featuring extremely low off-state current is proposed. Using the flip-flop, 32-bit processor has been fabricated 350-nm Si/180-nm semiconductor technology, demonstrated data shutdown in 1.5 clock cycles at 1.77 nJ, recovery 2.5 cycles, for least day. According to simulation results, fast...
We have formed heterogeneous oxide semiconductor FETs (OSFETs) in one planar FET layer and two vertical (VFET) layers over Si by monolithically stacking OSFETs on top of CMOS. Formation IOSIC DRAM memory cells the VFET a primary sense amplifier (1st SA) has realized with different functions such as switching signal amplification for first time. As result, special features, which are three-dimensional monolithic long date retention, implemented.
Aiming to reduce the area of a ferroelectric random access memory (FeRAM), we fabricated an FeRAM having 1T1C configuration by using c-axis aligned crystalline In-Ga-Zn-O field-effect transistor, which call OSFET, with high breakdown voltage. A combination OSFET L/W 60 nm/60 nm and single damascene capacitor (FECap) attained FE-Cap reduction 0.06 μm2 per cell. The achieved write time 10 ns, rewriting endurance 109 cycles, data retention 100 min at 85°C. is optimal selector element for...
The progress in emerging memory featuring indium–gallium–zinc oxide semiconductor field-effect transistors (OSFETs) is overviewed. An OSFET exhibits an extremely low off-state current the order of zeptoamperes (zA or 10-21 A). process embedded into a conventional CMOS process, and stacked over SiFET. OSFET-based achieves high speed, voltage writing endurance. Using enables low-power ULSI such as with very refresh rate processor without any leakage power. Oxide key device that ULSI, it can...
A dynamic oxide semiconductor random access memory (DOSRAM) array that achieves reduction in storage capacitance (Cs) and decrease refresh rate has been fabricated by using a c-axis aligned crystalline (CAAC-OS) transistor (L = 60 nm) with an extremely low off-state current. We have confirmed this array, composed of cells include CAAC-OS W/L 40 nm/60 nm InGaZnO 3.9 fF capacitor, operates write read times 5 ns. Therefore, DOSRAM can ensure sufficient Cs while maintaining operation speed...
As the number of devices connected to Internet increases, servers and mobile must process increasingly large volumes data, also accommodate increasing demand for high-speed large-capacity working memory keeping power consumption low. This need is being fulfilled by emerging devices, such as resistive RAM, phase-change MRAM [1], which realize high-speed, high-density nonvolatile memory, significantly enhancing performance CPUs with integrated memories.
A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc (CAAC-IGZO) and Cortex-M0 core flip-flops with CAAC-OS is fabricated. The M0 can retain data the during power-off; thus, they perform power gating (PG) time 100 ns recovery 10 clock cycles (including restoration (100 ns)). Further, memory cell area performance in combining 45-nm Si are estimated to have negligible overhead.
SRAM with backup circuits using a crystalline oxide semiconductor (OS) (e.g., c-axis aligned (CAAC-OS) typified by CAAC In-Ga-Zn (CAAC-IGZO)) is reported. Results of cell-level simulation based on 45-nm Si/100-nm OS process technology show time 3.9 ns, recovery 2.0 and break-even 21.7 ns. The OS-SRAM cell can replace standard-SRAM without area overhead, which does not significantly affect normal operation. A 32-bit microprocessor test chip (350-nm Si/180-nm technology) cache memory including...
As leakage power continues to increase when transistor sizes are downscaled, it becomes increasingly hard achieve low consumption in modern chips. Normally-off processors use state-retention and non-volatile circuits make gating more efficient with less static power. In this paper, we propose two novel flip-flop designs based on a parallel series retention circuit architectures utilizing crystalline indium gallium zinc oxide transistors, which can state zero To demonstrate the application of...
This paper reports the validation of our prototyped memory operating with 1.8-V power supply and low stand-by power, using 60-nm c-axis-aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) field-effect transistors (FETs). Its operation evaluation verified that a reduction in driving voltage is enabled by application negative as (VSSL) word line. A negative-voltage generator uses CAAC-IGZO FETs comparator circuit. The total including consumed additional small 120 nW, which revealed simulation...
We prototyped a 228 KB oxide semiconductor memory utilizing field-effect transistors with c-axis-aligned crystalline (CAAC-OSFETs) and evaluated its tolerance to hard errors caused by X-rays soft heavy-ion beams. Evaluation results demonstrate that the OS has radiation high enough operate properly even in space environments.