A5004949394- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Electrostatic Discharge in Electronics
- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- 3D IC and TSV technologies
- Interconnection Networks and Systems
- Parallel Computing and Optimization Techniques
- Electromagnetic Compatibility and Noise Suppression
- Quantum and electron transport phenomena
- Magneto-Optical Properties and Applications
- Pigment Synthesis and Properties
- Physics of Superconductivity and Magnetism
- Wireless Power Transfer Systems
- Magnetic Field Sensors Techniques
- Superconductivity in MgB2 and Alloys
- Full-Duplex Wireless Communications
- Photonic Crystal and Fiber Optics
- Lightning and Electromagnetic Phenomena
- Laser-Matter Interactions and Applications
- Photonic and Optical Devices
- Electromagnetic Simulation and Numerical Methods
- Surface Roughness and Optical Measurements
- Embedded Systems Design Techniques
Renesas Electronics (Japan)
2004-2023
National Yang Ming Chiao Tung University
2022
University of Virginia
2022
Carnegie Mellon University
2022
Nagoya University
2022
Moscow Institute of Thermal Technology
2022
Texas Instruments (United States)
2022
University of Notre Dame
2022
Cornell University
2022
University of Pavia
2022
We propose a new design scheme to improve the SRAM read and write operation margins in presence of large Vth variability. By applying this 0.494 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell with beta ratio 1, which is an aggressively small size, we can achieve high-yield 8M-SRAM for wide range value using 65 nm LSTP CMOS technology
This paper presents power management and low techniques of our heterogeneous quad/octa-core mobile application processor (AP). AP has a combination high-performance 2 GHz cores energy-efficient 1 cores. The maximum performance in the octa-core configuration is 35,600 DMIPS. key design highlights are as follows. 1) Using dedicated PLL H-tree clock CPU achieves both operation reduced dynamic power. 2) A low-leakage SRAM 28 nm HPM process used leakage current peripheral circuits macro optimized...
We propose an on-die aging monitor based on ring-oscillator (RO) which measures bias-temperature-instabilities (BTI) and AC hot-carrier-infection (HCI). The consists of a symmetric RO (SRO) asymmetric (ASRO). effect NBTI PBTI can be separated by focusing the difference in sensitivity observed SRO ASRO under DC stress condition. In addition, speed degradation caused AC-HCI is monitored because unbalanced delay with long/short transition has high against stress. A test chip including both...
An increase in bias currents supplied to single-flux-quantum (SFQ) circuits is a rising problem building large-scale integrated SFQ circuits, because the magnetic fields generated by and ground return affect circuit operation. Current recycling technique, which can drastically reduce total current of expected be very effective solution for circuits. To realize signal transmission between logic located on different planes required. Two types inductively coupled pulse transfer were examined...
We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area 8T-DP-cell and keeps cell stability. A priority row decoder circuit shifted bit-line eliminates conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. obtain 0.71mum <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> 8T-DP-cell, which size is 1.44times larger than 6T-single-port (SP)
Experimental results of the 4-port nonreciprocal band-stop-pass filter and tunable resonance type circulator with properties are reported, theory new circuit is discussed. The operates over a two-octave frequency range about one-octave range.
We propose an on-chip bias temperature instabilities (BTI) monitor by using standard cell based unbalanced ring-oscillator (RO). The consists of NAND and NOR with extremely large difference in drive strength, which enables 4.2x sensitivity to BTI compared normal INV RO. This originates not only from accentuation the degraded stage small strength dominant delay but also ΔVth improvement stacked transistors increasing output transition time. In addition, our proposal allows either one negative...
This paper presents an analysis of impact local bias temperature instability (BTI) by measuring Ring-Oscillators (RO) with short stage and its on Logic circuit SRAM. The evaluation result BTI variation based RO at a test chip fabricated in 7 nm FinFET process shows that the standard deviation NBTI Vth degradation is proportional to square root mean value (μ(Δ Vthp)) any stress time, flavors various recovery condition. Based these measurement result, we present logic considering measured...
We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It designed be as convenient an SRAM for measurement imitates LSI. implemented 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it effortless detect failure locations layers by fail bit maps. Owing this we can significantly shorten development period advanced technology.
Abstract The high‐speed characteristics and off of a novel transistor with hot‐electron launcher transit layer an intrinsic semiconductor whose current is controlled by insulated gate are evaluated Monte Carlo simulation. dependences the cutoff frequency f T on insulator thickness, collector bias voltage, length clarified. For optimum structure consisting InP/InGaAs/W as emitter/transit layer/collector, Au bisbenzocyclobutene (BCB) surrounding material, 1.4 THz at density 1.6 MA/cm 2 . can...
The worldwide demand for high-performance mobile or car infotainment application processors (AP) is increasing. This coexists with the need low power to achieve long battery life and avoid thermal runaway. A heterogeneous CPU configuration an effective solution. proposed quad/octa-core AP has a combination of 2GHz cores energy-efficient 1GHz cores. maximum performance in octa-core 35600 DMIPS. key design highlights are: 1) Using dedicated PLL H-tree clock achieves both operation reduced...
We measured ultra-long term BTI-induced degradation of 7-nm ring oscillators (ROs) using a measurement system controlled by an FPGA and microcontroller unit. The ambient temperature the supply voltage were set to 125°C nominal 0.75 V. results showed that even over very long period around 5 months (le7 s), RO oscillation frequency continuously degraded with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$t^{n}$</tex> , propose model in which BTI...
The authors propose an on-chip NBTI, PBTI and HCI monitor by using standard cell based unbalanced RO at 7 nm Fin-FET process. NBTI consists of two ROs; one is NBTIRO the other R-NBTI-RO with reversed order NBTI-RO. gets fast after stress where as ROs degraded. As a result, 6.2x sensitivity compared normal INV-RO negligibly small are achieved. achieved in similar manner. In monitor, degradation 3.6x emphasized simulating worst-case waveform logic circuit drive strength configuration INV cell....
Ultrafast operation of a transistor using ballistic electron concepts and its fabrication feasibility are shown by Monte Carlo simulation experiment, respectively. The consists InP/GaInAs heterojunction launcher 20 nm-width subsequent propagation layer 80 nm-length intrinsic GaInAs. Schottky metal gates attached on both sides the biased in forward direction so that potential barriers at junctions flattened hot electrons extracted from launcher. Hot velocity is as fast 7-8 × 107 cm/s through...
We propose a novel mobility measurement method which can be applied to industrial sized MOSFETs. The variation caused by Shallow Trench Isolation (STI) stress is evaluated directly. Extracted piezoresistance coefficients in the inversion layer are close their counterparts bulk silicon. effect model like that incorporated into BSIM4.3.0 verified adequately predict behavior. Additionally, we have observed for first time <100> channel MOSFETs less sensitive STI than <110> along Therefore, CMOS...
The general formulas for both 4-port magnetic-resonator circulators and 2-port bandpass filters (BPF's) are given. effects of the circuit structure physical properties resonator on characteristics investigated. maximum dissipation loss is just one half input power. Contrary to results shown in previous reports, it understood that a given resonator, there exists an optimum value external Q also polycrystalline magnetic may be useful nonreciprocal circuit, if product unloaded saturation...
An embedded SRAM power management scheme using 16 nm FinFET technology is demonstrated in automotive infotainment SoCs. By introducing write-assist circuit technique, can operate down to 0.5 V wide voltage range, achieving DVFS for efficient saving. Fast resume standby mode also developed reducing the leakage of L1 cache under 2 GHz CPU operation. We confirmed that proposed thermal control be protected by runaway failure.
We have developed a power-gating technique for mobile processor in 28-nm HKMG technology. The proposed EM-tolerant 1.8V I/O NMOS power switch reduces the standby to 1/641× and achieves 79% channel utilization without weakening EM immunity. active leakage of dual CPU cores can be reduced by 45 mW single core operation mode with rapid 1.4-μs wakeup time full operation. A is designed fabricated technique. Estimated chip 123 μW, resulting one order magnitude reduction compared conventional...
This paper presents an analysis methodology of the impact Local Layout Effect (LLE) bias temperature instability (BTI) on logic circuits by measuring Ring-Oscillators (RO) consist many kinds standard cells and shows its measurement result in a 10nm FinFET process. The measured delay degradations all ROs are well correlated with estimated one without considering LLE BTI maximum error rates is -16% +13%. recovery effect also evaluated there no obvious cell type dependency. would be useful for...