A5057901469- Low-power high-performance VLSI design
- VLSI and Analog Circuit Testing
- Radiation Effects in Electronics
- Semiconductor materials and devices
- VLSI and FPGA Design Techniques
- Embedded Systems Design Techniques
- Advancements in Semiconductor Devices and Circuit Design
- 3D IC and TSV technologies
- Advancements in Photolithography Techniques
- Advanced Photonic Communication Systems
- Optical Network Technologies
- Parallel Computing and Optimization Techniques
- Formal Methods in Verification
- Power Line Communications and Noise
- Advancements in PLL and VCO Technologies
Synopsys (Switzerland)
2024
University of Thessaly
2018-2023
Özyeğin University
2022
Politecnico di Milano
2022
University of Bremen
2022
University of California, Santa Barbara
2022
University of Patras
2022
Bridge University
2022
Yale University
2020
The University of Texas at Austin
2020
As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are resistive, signals no longer resemble saturated ramps, gate input pins exhibit a significant Miller effect. Over recent years, the semiconductor industry has adopted current source models (CSMs) for modeling. Industrial models, however, precharacterized assuming capacitive loads, which poses challenges to approximation of highly resistive...
In this work, we present an Asynchronous Static Timing Analysis (ASTA) EDA methodology for cyclic, Control Circuits. Our operates using Graph-based (GBA) principles, as conventional synchronous GBA STA, is fast, and pessimistically computes Critical Cycle(s), instead of Paths, without cycle cutting. ASTA flow supports industrial Libraries, Verilog input multiple PVT corners. Gate timing arc delay/slew computation, input/output environment constraints, path delay propagation, are implemented...
Abax is a modern version of the classical Abacus, minimum displacement, greedy legaliser. supports single-tier 2D or 3D legalisation for multiple, logic-on-logic 3D-IC tiers, efficient look-ahead intermediate Global Placement (GP) iterations, Hard Macros, Blockages, row density constraints and multiple local cell displacement functions orderings. For 3D-IC, can produce multi-tier placements by performing Legalisation-based Partitioning. Look-ahead Legalisation, two new cost functions,...
In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our uses Graph-based (GBA) STA principles, is fast, able compute setup or hold slacks sequential elements, and operates without cycle cutting. Industrial Libraries, Verilog input multiple PVT corners are supported. To perform the circuit portion, Event Model, live 1-bounded Signal...
In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, and secondly propagation may not be upper bounded across multiple cut points in same cycle. The use an Asynchronous (ASTA) engine, which does cycles, properly bounds slews a possible solution, can indeed serve bound over SPICE...
The manufacturing of modern Integrated Circuits (IC), resistant to faults caused by ionising radiation, has become quite challenging due the rapid advancement VLSI technology. Existing literature employs a combination simulation-based and analytical methods achieve efficient Single Event Transients (SET) analysis. In this work, we propose novel Electronic Design Automation (EDA) analysis approach for SETs, called UPSET. UPSET can handle circuits with thousands gates since it relies on...
In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, and secondly propagation may not be upper-bounded across multiple cut points in same cycle. The use an ASTA engine, which does cycles, properly bounds slews a possible solution, can indeed serve upper bound over SPICE, transistor level similations....
Process variation has proven to be one of the higher impacting factors in modern Application-Specific Integrated Circuit (ASIC) flows Quality Results (QoR). On hand, excessive MOSFET shrinking, combination with less potent metallization layers shrinking ability at cutting edge technology nodes, rendered process effects more and pronounced. other ever-increasing market competition between hi-tech semiconductor companies promoted adoption immature, emerging which are not adequately calibrated...
The manufacturing of modern Integrated Circuits (ICs), resistant against faults caused by ionising radiation, has become quite challenging due to the rapid advancement VLSI technology. Additionally, Radiation Hardening process, which involves making electronic cells and circuits damage or induced deviates from conventional design flow. Thus, it generally suffers insufficient support industrial EDA tools. RADPlace is an academic timing-driven detailed placement algorithm that ensures spacing...
The ever increasing demand for reliable microelectronic systems in the presence of radiation, combined with continuous shrinking CMOS technologies, has rendered impact radiation-induced voltage glitches, known as Single Event Transients (SETs), more and critical. In order to mitigate such errors, analysis circuit radiation immunity these effects is mandatory. This is, nowadays, performed either manufacturing irradiation experiments, which prohibitively expensive or TCAD SPICE simulations,...