A5028340901- Parallel Computing and Optimization Techniques
- Distributed and Parallel Computing Systems
- Cloud Computing and Resource Management
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Embedded Systems Design Techniques
- Real-Time Systems Scheduling
- VLSI and Analog Circuit Testing
- CCD and CMOS Imaging Sensors
- Advanced Data Storage Technologies
- Error Correcting Code Techniques
- Neural Networks and Reservoir Computing
- Advanced Wireless Communication Techniques
- Interconnection Networks and Systems
- Nuclear and radioactivity studies
- Wireless Body Area Networks
- Antenna Design and Analysis
- Wireless Communication Security Techniques
- Cooperative Communication and Network Coding
- Advanced MIMO Systems Optimization
University of Arizona
2019-2024
Politecnico di Milano
2022
University of Bremen
2022
University of California, Santa Barbara
2022
University of Patras
2022
Bridge University
2022
Özyeğin University
2022
University of Dhaka
2014-2016
In this work, we present a C ompiler-integrated, E xtensible D omain Specific System on Chip R untime (CEDR) ecosystem to facilitate research toward addressing the challenges of architecture, system software, and application development with distinct plug-and-play integration points in unified compile time runtime workflow. We demonstrate utility CEDR Xilinx Zynq MPSoC-ZCU102 for evaluating performance pre-silicon hardware trade space SoC configuration, scheduling policy workload complexity...
Neuromorphic architectures have been introduced as platforms for energy efficient spiking neural network execution. The massive parallelism offered by these has also triggered interest from non-machine learning application domains. In order to lift the barriers entry hardware designers and developers we present RANC: a Reconfigurable Architecture Computing, an open-source highly flexible ecosystem that enables rapid experimentation with neuromorphic in both software via C++ simulation FPGA...
Domain-specific systems-on-chip (DSSoCs) aim at bridging the gap between application-specific integrated circuits (ASICs) and general-purpose processors. Traditional operating system (OS) schedulers can undermine potential of DSSoCs since their execution times be orders magnitude larger than time task itself. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines benefits fast (low-overhead) scheduler slow (sophisticated, high-performance but...
Wireless Body Area Network (WBAN) is one of the latest technologies in wireless communication, and being widely studied for its applications military, healthcare, sports, other sectors. In this paper transmission coefficients S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> are measured several on-body radio channels effects two different body structures on path loss determined. Considering static position laboratory, measurements...
As the computing landscape evolves, system designers continue to explore design methodologies that leverage increased levels of heterogeneity push performance within limited size, weight, power, and cost budgets. One such methodology is build Domain-Specific System on Chips (DSSoCs) promise productivity through narrowed scope their target application domain. In previous works, we have proposed CEDR, an open source, unified compilation runtime framework for DSSoC architectures allows...
Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored target domain minimize task execution times power consumption. Traditional operating system (OS) schedulers can diminish potential of DSSoCs, as their be orders magnitude larger than time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines...
Energy is the prime need for development of a country and its substantial economic growth. Over all forms energies, nuclear energy most prominent, powerful challenging source. Despite effectiveness this energy, hazardous radiation effects can enormously be dangerous destructive. Our study mainly focuses on comparative overviews aspects Bangladesh, discussions environment living objects health. The paper also suggests some challenges to meet probable future shortcomings Nuclear Power Plant in...
Diversely Heterogeneous System-on-Chips (DH-SoC) are increasingly popular computing platforms in many fields, such as autonomous driving and AR/VR applications, due to their ability effectively balance performance energy efficiency. Having multiple target accelerators for concurrent workloads requires a careful runtime analysis of scheduling. In this study, we examine scenario that mandates several concerns be carefully addressed: 1) exploring the mapping various heterogeneous optimize...
Open-source simulation tools play a crucial role for neuromorphic application engineers and hardware architects to investigate performance bottlenecks explore design optimizations before committing silicon. Reconfigurable Architecture Neuromorphic Computing (RANC) is one such tool that offers ability execute pre-trained Spiking Neural Network (SNN) models within unified ecosystem through both software-based FPGA-based emulation. RANC has been utilized by the community with its flexible...
Open-source simulation tools play a crucial role for neuromorphic application engineers and hardware architects to investigate performance bottlenecks explore design optimizations before committing silicon. Reconfigurable Architecture Neuromorphic Computing (RANC) is one such tool that offers ability execute pre-trained Spiking Neural Network (SNN) models within unified ecosystem through both software-based FPGA-based emulation. RANC has been utilized by the community with its flexible...
We present a modular FPGA-based testbed to accelerate the study of low-density parity-check codes (LDPC). This is composed controller, codeword generator, noise random number LDPC decoder, and statistical analysis modules. The decoder module replaceable enable development or new existing hard-decision-based decoders. demonstrate our testbed's ability reduce timescale error correction pattern through case studies involving Gallager B (GaB) Probabilistic (PGaB) algorithms. contextualize...
The Internet of Things infrastructure connects a massive number edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient programmable implementations error correction codes (ECCs) decoders. algorithmic flow ECCs concurrent accumulation comparison types operations are innately exploitable by neuromorphic architectures execution—an area that is relatively unexplored outside machine learning...
This article presents FALCON, a full-system domain-specific system-onchip emulation platform that enables presilicon power and performance estimation of these platforms to provide support for early functional validation software development.
Domain-specific systems-on-chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, while hardware accelerators tailored target domain minimize task execution times power consumption. Traditional operating system (OS) schedulers can diminish potential of DSSoCs as their be orders magnitude larger than time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines...
Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase computation complexity task scheduling problem compared to homogeneous architectures. Latency a software-based scheduler with increased heterogeneity level in terms number types PEs creates necessity deploying as an overlay processor hardware be able make decisions rapidly enable deployment real-life applications on SoCs. In this study we present design trade-offs involved for...
As the computing landscape evolves, system designers continue to explore design methodologies that leverage increased levels of heterogeneity push performance within limited size, weight, power, and cost budgets. One such methodology is build Domain-Specific System on Chips (DSSoCs) promise productivity through narrowed scope their target application domain. In previous works, we have proposed CEDR, an open source, unified compilation runtime framework for DSSoC architectures allows...
Value-based resource management heuristics, which are traditionally deployed in heterogeneous HPC systems, maximize system productivity by assigning resources to each job based on its priority and estimated value gain relative job's completion time. We investigate the utility of value-based at SoC scale demonstrate ability make effective scheduling decisions for time-constrained jobs oversubscribed systems where shared multiple users applications arrive dynamically. The proposed approach...
The Internet of Things infrastructure connects a massive number edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient programmable implementations Error Correction Codes (ECC) decoders. algorithmic flow ECCs concurrent accumulation comparison types operations are innately exploitable by neuromorphic architectures energy efficient execution -- area that is relatively unexplored outside machine...
Non-uniform performance and power consumption across the processing elements (PEs) of heterogeneous SoCs increase computation complexity task scheduling problem compared to homogeneous architectures. Latency a software-based scheduler with increased heterogeneity level in terms number types PEs creates necessity deploying as an overlay processor hardware be able make decisions rapidly enable deployment real-life applications on SoCs. In this study we present design trade-offs involved for...