A5007504207- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- 2D Materials and Applications
- Semiconductor materials and interfaces
- Advanced Memory and Neural Computing
- Thin-Film Transistor Technologies
- MXene and MAX Phase Materials
- ZnO doping and properties
- Electronic and Structural Properties of Oxides
- Copper Interconnects and Reliability
- Nanowire Synthesis and Applications
- Silicon and Solar Cell Technologies
- Ga2O3 and related materials
- Silicon Carbide Semiconductor Technologies
- GaN-based semiconductor devices and materials
- Ferroelectric and Piezoelectric Materials
- Electronic Packaging and Soldering Technologies
- 3D IC and TSV technologies
- Chalcogenide Semiconductor Thin Films
- Multiferroics and related materials
- Acoustic Wave Resonator Technologies
- Advanced Welding Techniques Analysis
- Radiation Effects in Electronics
The University of Texas at Dallas
2016-2025
Defence Research and Development Canada
2023
Arizona State University
2020
The University of Texas at Austin
2013-2020
University College Cork
2017
Texas Instruments (United States)
2017
IBM Research - Thomas J. Watson Research Center
2013
Xi'an University of Science and Technology
2010
Nicholls State University
2008
Semtech (United States)
2008
We report on atomic layer deposited Hf0.5Zr0.5O2 (HZO)-based capacitors which exhibit excellent ferroelectric (FE) characteristics featuring a large switching polarization (45 μC/cm2) and low FE saturation voltage (∼1.5 V) as extracted from pulse write/read measurements. The in HZO is achieved by the formation of non-centrosymmetric orthorhombic phase, enabled TiN top electrode (TE) having thickness at least 90 nm. films are room temperature annealed 400 °C an inert environment for 1 min...
An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt depends on rare earth (RE) type and diffusion Si∕SiOx∕HfSiON∕REOx/metal nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This ordering very similar to the trends dopant electronegativity (EN) (dipole charge transfer) ionic radius (r) separation) expected for a interfacial mechanism. The resulting dependence RE allows...
We report on the effect of Hf0.5Zr0.5O2 (HZO) film thickness ferroelectric and dielectric properties using pulse write/read measurements. HZO films thicknesses ranging from 5 to 20 nm were annealed at 400 °C for 1 min in a nitrogen ambient be compatible with back-end line thermal budget. As decreases, low-voltage operation (1.0 V or less) can achieved without dead layer effect, although switching polarization (Psw) tends decrease due smaller grain size. Meanwhile, 20-nm-thick prepared under...
The influence of Hf-based dielectrics on the underlying SiO2 interfacial layer (IL) in high-k gate stacks is investigated. An increase IL dielectric constant, which correlates to an positive fixed charge density IL, found depend starting, pre-high-k deposition thickness IL. Electron energy-loss spectroscopy and electron spin resonance spectra exhibit signatures high-k-induced oxygen deficiency consistent with electrical data. It concluded that high temperature processing generates vacancies...
Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It suggested that the electron occurs through a two-step process: resonant tunneling of injected into preexisting defects (fast trapping) and thermally activated migration trapped electrons to unoccupied traps (slow trapping). Characteristics extracted based on proposed model are good agreement with calculated properties negatively charged oxygen vacancies. The successfully describes low-temperature...
Border traps and interface in HfO2/few-layer MoS2 top-gate stacks are investigated by C–V characterization. Frequency dependent data shows dispersion both the depletion accumulation regions for devices. The border trap density is extracted with a distributed model, analyzed using high-low frequency multi-frequency methods. physical origins of appear to be caused impurities/defects layers, performing as band tail states, while associated dielectric, likely consequence low-temperature...
In this letter, the ferroelectric (FE) properties of 5-nm-thick Hf0.5Zr0.5O2 (HZO) films deposited by atomic layer deposition have been investigated. By reducing HZO film thickness to 5 nm, low-voltage operation (1.0 V) HZO-based capacitor was achieved while maintaining a remnant polarization (Pr) about 10 μC/cm2 (i.e., 2Pr 20 μC/cm2). Meanwhile, in order form an orthorhombic phase, which is responsible for FE properties, rapid thermal annealing process performed after TiN top electrode...
A high quality Al2O3 layer is developed to achieve performance in top-gate MoS2 transistors. Compared with field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved high-k backside devices. forming gas anneal found enhance device due reduction charge trap density of dielectric. The major improvements are ascribed dielectric screening layer. Top-gate devices built upon these stacks exhibit near-ideal ∼69 mV/dec Y-Function extracted carrier...
The pulsed current-voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - xmlns:xlink="http://www.w3.org/1999/xlink">V</i> ) measurement technique with pulse times ranging from ~17 ns to ~6 ms was employed study the effect of fast transient charging on threshold voltage shift Delta <sub xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> MOSFETs. extracted values are found be strongly dependent band bending dielectric stack defined by...
The total ionizing dose (TID) response of double-gate SiGe- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">${{\rm SiO}_2}/{{\rm HfO}_2} \ p$</tex></formula> MOS FinFET devices is investigated under different device bias conditions. Negative irradiation leads to the worst-case degradation due increased hole trapping in HfO}_2}$</tex></formula> layer, contrast what typically observed for with...
High quality sub-10 nm high-k dielectrics are deposited on top of MoS2 and evaluated using a dual-gate field effect transistor configuration. Comparison between top-gate HfO2 an Al2O3/HfO2 bilayer shows significant improvement in device performance due to the insertion thin Al2O3 layer. The results show that buffer layer improves interface by effectively reducing net fixed positive oxide charge at MoS2/high-k dielectric interface. Dual-gate sweeping, where both back-gate swept...
The benefits of O2 plasma exposure at the contact regions dual-gate MoS2 transistors prior to metal deposition for high performance electron contacts are studied and evaluated. Comparisons between devices with without demonstrate significant improvements due formation a high-quality interface low Schottky barrier (∼0.1 eV). Topographical interfacial characterizations used study on from initial exfoliated surface through photolithography process Ti deposition. Fermi level pinning near...
Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO/sub 2//HfO/sub 2//TiN stacks. Using gate stacks varying thicknesses of the interfacial 2/ layer (IL) or high-/spl kappa/ and analysis for frequency-dependent CP data developed address depth profiling, authors have determined that defect range practical importance occurs primarily within IL on as-grown "precursor" defects most likely caused by overlaying...
A methodology to analyze charge pumping (CP) data, which allows positions of probing traps in the dielectric be identified, was applied extract spatial profile SiO2∕HfO2 gate stacks. The results suggest that accessible by CP measurements a wide frequency range, down few kilohertz, are located within or near interfacial SiO2 layer rather than bulk high-k film.
We apply a systematic approach to identify high-k/metal gate stack degradation mechanism. Our results demonstrate that the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interfacial layer controls overall and breakdown of high-k stacks stressed in inversion. Defects contributing are associated with high-k/metal-induced oxygen vacancies layer.
An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO gate stacks. This indicates that the accessible by CP frequency range down a few kilohertz are located primarily within layer HfO /SiO interface region. The trap density increases closer high-kappa dielectric, while profile as function distance from...
The electronic properties of the HfO2/MoS2 interface were investigated using multifrequency capacitance–voltage (C–V) and current–voltage characterization top-gated MoS2 metal–oxide–semiconductor field effect transistors (MOSFETs). analysis was performed on few layer (5–10) MOSFETs fabricated photolithographic patterning with 13 8 nm HfO2 gate oxide layers formed by atomic deposition after in-situ UV-O3 surface functionalization. impedance response stack indicates existence specific defects...
The discovery of ferroelectricity in HfO2-based materials 2011 provided new research directions and opportunities. In particular, for atomic layer deposited Hf0.5Zr0.5O2 (HZO) films, it is possible to obtain homogenous thin films with satisfactory ferroelectric properties at a low thermal budget process. Based on experiment demonstrations over the past 10 years, well known that HZO show excellent when sandwiched between TiN top bottom electrodes. This work reports comprehensive study effect...
Abstract Two-dimensional (2D) semiconductors have received a lot of attention as the channel material for next generation transistors and electronic devices. On other hand, insulating 2D gate dielectrics, possible materials dielectrics in transistors, little attention. We performed an experimental study on bismuth oxychloride, which is theoretically proposed to good dielectric properties. High-quality oxychloride single crystals been synthesized, their high crystallinity spatial homogeneity...
Analysis of electrical and scanning transmission electron microscopy (STEM) energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO2 layer modifies the oxygen content latter resulting in reduction oxide band gap correspondingly increasing its k value. High-k deposition thinner films, below 1.1 nm, may lead to formation highly deficient amorphous interfacial adjacent Si substrate. This was identified as an important factor contributing mobility degradation...
A single-pulse technique, with a wide range of pulse times, has been applied to study positive bias temperature instability in high-k nMOSFETs. It is shown that the charging phenomenon includes both fast and slow electron trapping processes rather well-defined characteristic which differ by six orders magnitude. On other hand, poststress charge relaxation cannot be described simple detrapping process, makes identifying dominant mechanism complicated.
Transition metal dichalcogenides (TMDs) have attracted intensive attention due to their atomic layer-by-layer structure and moderate energy bandgap. However, top-gated transistors were only reported in a limited number of research works, especially with high-k gate dielectric that are thinner than 10 nm because dielectrics difficult deposit on the inert surface sulfide-based TMDs. In this work, authors fabricated characterized top-gated, few-layer MoS2 an 8 HfO2 dielectric. The show cleaning...