A5068851524- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices
- Silicon Carbide Semiconductor Technologies
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Stellar, planetary, and galactic studies
- Astronomy and Astrophysical Research
- Low-power high-performance VLSI design
- Semiconductor materials and interfaces
- Radio Frequency Integrated Circuit Design
- Silicon and Solar Cell Technologies
- Astrophysics and Star Formation Studies
- Thin-Film Transistor Technologies
- Nanowire Synthesis and Applications
- Structural Behavior of Reinforced Concrete
- Digital Holography and Microscopy
- Radiation Effects in Electronics
- Astronomical Observations and Instrumentation
- Advanced Memory and Neural Computing
- Cell Image Analysis Techniques
- Fuel Cells and Related Materials
- Atmospheric Ozone and Climate
- TiO2 Photocatalysis and Solar Cells
- Mechanical Behavior of Composites
- Graphene research and applications
Delft University of Technology
2023-2025
Korea University
2012-2023
Sejong University
2021
Guangzhou Institute of Geography
2020
Hainan Normal University
2020
Pohang University of Science and Technology
2019
Tsinghua University
2013-2017
Institute of Microelectronics
2013-2015
Texas A&M University
2008
University of Florida
2003-2005
The abnormal corner effects on channel current in nanoscale triple-gate MOSFETs are examined via two-dimensional (2-D) numerical simulations and quasi-2-D analysis. Heavy body doping [for threshold voltage (V/sub t/) control with a polysilicon gate] is found to underlie the effects, which can hence be suppressed, irrespective of shape corners, by leaving undoped, relying metal gate proper work function for V/sub t/ control. Short-channel tend ameliorate but need ad hoc suppression remains.
The feasibility of triple-gate MOSFETs (TGFETs) for nanoscale CMOS applications is examined with regard to short-channel effects (SCEs) and gate-layout area. Three-dimensional numerical simulations TGFETs reveal that much more stringent body scaling SCE control needed undoped bodies relative doped ones (which are not viable devices) due the suppression corner current conduction technologically advantageous) in former. When scaled adequate control, further analysis shows generic TGFET suffers...
Parasitic gate–source/drain (G–S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G–S/D underlap. Analytical modeling of the outer inner components developed verified simulations; BOX-fringe component modeled for single-gate fully depleted silicon-on-insulator MOSFETs. With new implemented UFDG, our...
The speed performance of a double-gate (DG) FinFET CMOS with gate-source/drain (G-S/D) underlap is investigated using 2-D device and mixed-mode circuit simulation. By optimizing the G-S/D underlap, we demonstrate that fin thickness DG can be significantly increased up to physical gate length without degrading compared conventional overlap structure, where needs less than one-half control short-channel effects. Such an increase in combined relaxed requirement for abruptness source/drain...
The authors report on the novel MOSFETs that were fabricated thin relaxed Ge epitaxial layers grown Si substrates. With controlled epi-Ge thickness, selectively activated shallow source/drain (S/D) junctions are formed using low dopant activation energy of Ge. determine effective S/D junction depth by activating implantations only in layers, while suppressing Low leakage current and capacitance also achieved forming substrates as well with thickness. this technique applied to Ge-on-Si...
An explicit analytical model for long-channel double-gate junctionless transistors is presented in each operation mode: 1) full depletion; 2) partial and 3) accumulation. The proposed calculates potentials, electric fields, mobile charges, drain current without any implicit function or special functions. results obtained with the agree well a 2-D technology computer-aided design simulation all modes of various device structures. Furthermore, physical insight provided into reducing...
view Abstract Citations (50) References (55) Co-Reads Similar Papers Volume Content Graphics Metrics Export Citation NASA/ADS Modal Approach to the Morphology of Spiral Galaxies. III. Application Galaxy M81 Lowe, S. A. ; Roberts, W. Yang, J. Bertin, G. Lin, C. The modal approach morphology spiral galaxies is applied galaxy NGC 3031 (M81) demonstrate how shape pattern, specifically that obtained by Elmegreen et al. for distribution stellar objects, may be used help with determination...
A new SOI MOSFET structure to reduce the floating body effect is proposed and successfully demonstrated. The key idea of that field oxide does not consume silicon film completely, so well contact can suppress potential increase in through remaining between buried oxide. measured results show suppressed as expected. This retains most advantages propagation delay conventional without instability. An additional advantage layout process are same those bulk CMOS.
The breakdown characteristics of the crystalline and amorphous hafnium (Hf) silicates have been studied using metal-insulator-metal capacitors. It is found that, although distribution time-dependent dielectric charge to (QBD) are affected by crystallization, primarily controlled electric field rather than fluence.
Abstract The total-dose-effects of gamma and proton irradiations on high-voltage silicon–germanium heterojunction bipolar transistors with the collector electrode elicited from backside substrate are investigated. Pre- post-radiation DC characteristics used to quantify dose tolerance two different irradiation sources. Measurement results indicate that devices exhibit a total up Mrad level. device response is indeed radiation source dependent can produce more significant damage than...
In this letter, the effects of TiN-induced strain engineering on device characteristics for a metal gate/high-k silicon-on-insulator fin-shaped field-effect transistors were studied. From convergent-beam electron-diffraction analysis and simulation study, 3-nm TiN electrode was found to lead significantly higher tensile stress Si substrate than 20-nm electrode. This high stress-induced fast bulk carrier generation results in transient current-time characteristics. Therefore, 3- electrodes...
Effects of γ-ray irradiation on short-channel effects (SCEs) in low-doped double-gate MOSFETs are experimentally examined for various fin widths and channel lengths. The different behavior the NMOS PMOS devices analyzed using three-dimensional (3-D) TCAD simulation. physical interpretation influence ionizing radiation SCEs multi-gate is provided. This successfully explains not only degradation NMOS, but also improvement subthreshold characteristics by irradiation.
view Abstract Citations (27) References (39) Co-Reads Similar Papers Volume Content Graphics Metrics Export Citation NASA/ADS A CO Study of Sharpless 171: Evidence for Interaction between the H II Region and Its Neighboring Molecular Cloud Yang, Ji ; Fukui, Yasuo Observations S171 region were made using J = 1-0 lines (C-12)O, (C-13)O, (C-18)O emission. The large-scale molecular gas distribution in its neighborhood has been mapped. Two dense clumps have revealed near young star cluster Be 59...
In this work, we studied the effect of high-pressure deuterium annealing (HPDA) on a p-type omega-gate nanowire field transistor by random telegraph noise (RTN) signal analysis. After HPDA under conditions 400 °C and 10 atm for 30 min, IOFF decreases 41.2% ION increases up to 5.4%. Also, subthreshold swing (SS) is reduced from 72 mV dec-1 70 dec-1. RTN analysis, multi-level single-level due passivation fast trap site HPDA. ΔID/ID also decreased 1.3 1.1 times at |VOV| = 0.2 V 0.4 V,...
An improved high-frequency small-signal model for SiGe HBTs under the off-state is presented in this paper. The proposed takes into account distribution characteristics of intrinsic transistor, link base region spacer, and extrinsic base-collector junction. equivalent circuit each separately derived using transmission line equation with reasonable approximations. Being different from previous models, resistance pushed inside internal node added to components collector emitter resistance. To...
1 Gbit SOI DRAM with a body-contacted (BC) MOSFET structure is successfully realized for the first time. The fabricated 1G has fully compatible process 0.17 /spl mu/m bulk CMOS technology except isolation process. key advantage of BC-SOI freedom from floating-body effect, since body-potential increase can be suppressed by well contact through remaining thin-silicon film beneath field oxide. several advantages, such as relatively high punchthrough voltage, drain-to-source breakdown voltage...