A5043022589- 3D IC and TSV technologies
- Electronic Packaging and Soldering Technologies
- Semiconductor materials and devices
- Copper Interconnects and Reliability
- Nanofabrication and Lithography Techniques
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Surface Polishing Techniques
- Additive Manufacturing and 3D Printing Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor Lasers and Optical Devices
- Microfluidic and Capillary Electrophoresis Applications
- Advanced MEMS and NEMS Technologies
- Heat Transfer and Optimization
- Advancements in Photolithography Techniques
- Semiconductor materials and interfaces
- Thin-Film Transistor Technologies
- Silicon and Solar Cell Technologies
- Manufacturing Process and Optimization
- X-ray Diffraction in Crystallography
- VLSI and Analog Circuit Testing
- Crystallization and Solubility Studies
- Surface Roughness and Optical Measurements
- Silicon Carbide Semiconductor Technologies
- Heat Transfer and Boiling Studies
- Surface and Thin Film Phenomena
Tokyo Institute of Technology
2015-2024
National Yang Ming Chiao Tung University
2019
National Institute of Technology, Suzuka College
2019
Nagoya University
2018
The University of Tokyo
2005-2014
Bunkyo University
2009-2014
Fujitsu (Japan)
1987-2004
Tokyo Electron (Japan)
1995
The main issue of Cu metallization is the electromigration through interface between and barrier or capping layer. To improve resistance at metal interface, insertion a glue layer which enhances adhesion onto under may be effective. wettability on Ru Ta layers was evaluated as index strength layers. wetting angle (43°) substrate three times lower than that (123°) after annealing. Lower indicates good property imply high resistance. better compared to can explained by concept lattice misfit....
Four-terminal conductivity measurements of damascene copper (Cu) wires with various widths have been performed using platinum-coated carbon nanotube (CNT) tips in a four-tip scanning tunneling microscope. Using CNT enabled the probe spacing to be reduced 70 nm, which is shortest interconnect wire achieved so far. The measured resistivity Cu increased as line width decreased and direct evidence individual grain boundary scattering was observed when varied on scale comparable size (∼200 nm).
Influence of the sidewall roughness in through-silicon via (TSV) on leakage currents has been studied. Micro steps along sidewall, so-called scalloping, formed by Bosch etching, are strongly related to between adjacent TSVs. Microcracks SiON barriers were observed TEM analysis and correlated with roughness. FEM simulations stress concentration clarified origin cracking. A non-Bosch etching process showed smooth surface we consider it be feasible for reliable TSV interconnects.
Ultrathin wafers, which enable the low-aspect-ratio through-silicon vias to be formed easily, are indispensable for bumpless three-dimensional (3D) stacking. To clarify thinning-induced damage in detail, atomic-level defects occurring during wafer thinning and due mechanical stress at microregions of fracture surface have been studied. Such was evaluated by µ-Raman spectroscopy, laser microscopy, transmission electron positron annihilation spectroscopy. Coarse (#320 grit) grinding causes a...
An ultra-thinning down to 4-μm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine and stress relief were optimized an atomic level vacancy less than 10-nm in depth at backside was formed successively. Thickness uniformity even after approximately 1-μm within wafer. No degradation terms retention characteristics distribution employing found ultra-thinning. This suggests that no...
The electromigration resistance of ultra-large scale integration (ULSI) Cu interconnects can be improved by inserting an adhesion promoter between and the diffusion barrier. A metallurgical survey was accomplished to select element having a good property. For adoption as interconnect material, it should have low resistivity not react with avoid increasing interconnects. Ru, Os, Mo, W, Ta satisfied above conditions. property these elements estimated lattice misfit concept. experimentally...
Diffusion behavior of Cu in through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vapor deposition (LT-PECVD) has been evaluated. Silicon oxynitride (SiON) barrier films were formed by LT-PECVD at 150 °C. diffusion rate was found to increase with decreasing film density. The critical density and thickness for prevention into Si substrate have estimated. In case a >60% the bulk value and/or >100 nm, no change electrical resistance stacked wafers...
The prospects of three-dimensional (3D) integration for Terabyte large scale using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) between wafers a second-generation alternative to the use micro-bumps Wafer-on-Wafer (WOW) technology. Ultra-thinning down 4 µm provides advantage small form factor, not only in terms total volume 3D ICs, but also aspect ratio Through-Silicon-Vias (TSVs). Our technology is classified into Via-Last, which...
Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW) for Tera-Scale Three-Dimensional Integration (3DI) is discussed. interconnects between wafers chips are a second-generation alternative to the use of micro-bumps WOW COW technologies. technologies BBCube can be used homogeneous heterogeneous 3DI, respectively. Ultra-thinning down 4 μm offers advantage small form factor, not only in terms total volume 3D ICs, but also aspect ratio Through-Silicon-Vias (TSVs)....
High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7-μm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded first time. The impact ultra thin on strained transistors Cu/low-k multilevel interconnects is described. Properties examined include Kelvin stack chain resistances Cu as well Ion-Ioff, threshold voltage shift, junction leakage transistors. It was found that electrical properties were not affected by bonding, thinning...
An ultra-thinning down to 2.6-μm with and without Cu contamination at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> atoms/cm xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness backside yield including retention characteristics is described. Thickness uniformity all wafers after thinning was below 2-μm within wafer. A degradation...
200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed 50-nm by Ultra Poligrind process, or completely with either Chemical Mechanical Planarization Dry Polish. For FRAM 9-μm, switching charge showed no change thinning process. CMOS logic 7-μm indicated neither m I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...
The rapid development of microfluidic technology has increased the demand for integration driving circuits in devices. We have proposed a novel on-chip electroosmotic (EOF) micropump integrated with high-voltage (11V) generator. 11V (49.8 V) generator is based on Dickson charge pump, which fabricated silicon-on-insulator (SOI) substrate by standard CMOS process, and isolation achieved MEMS post-processed deep trench isolation. size 49.8 V 425×353 μ m <sup...
Effect of via bottom cleaning process and electrical characteristics through-silicon (TSV) are investigated using 300-mm wafer-on-wafer (WOW) process. Several kinds method including wet dry were employed after TSV SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> liner etching It was found that sequential O plasma Ar sputtering provides the lowest resistance smallest variation among conditions we have evaluated, which is 0.3 times...
Thinning silicon wafers for stacking in limited space is essential the 3-D integration (3D!) technology of semiconductors. Due to lack research on mechanical properties thinned wafers, it difficult assess and improve reliability 3D! semiconductor devices. This article reports effects thickness crystallographic orientation tensile properties, such as Young's modulus, elongation, strength, wafer. Tensile a {100} wafer are measured using direct testing system, where digital image correlation...
Vacancy-type defects introduced by the grinding of Czochralski-grown Si wafers were studied using monoenergetic positron beams. Measurements Doppler broadening spectra annihilation radiation and lifetime positrons showed that vacancy-type in surface region (&lt;98 nm), major defect species identified as (i) relatively small vacancies incorporated dislocations (ii) large vacancy clusters. Annealing experiments concentration decreased with increasing annealing temperature range between 100...
Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, new lumped circuit model is proposed to simulate performance structure. Including actual contact resistance in model, integrity high-frequency signal can be accurately simulated. For 12-layer stacked TSV with plasma cleaning at bottom, transmission loss up 20 GHz lower than 2 dB. High eye height low jitter 3.2 Gbps show excellent for high bandwidth memory...
Chip-on-Wafer (COW) integration technology characterized by bumpless Cu interconnects between Si capacitor and re-distribution layer (RDL) was achieved for the first time. For fabricating a functional interposer using 300 mm wafer, embedded in with thin of adhesive mold resin. The were realized through silicon vias (TSVs), which are vertical upper lower to shorten interconnect length RDL. This 3D enables significant reduction package area (down 1/2) (below 1/100).