A5059645690- Advancements in PLL and VCO Technologies
- Radio Frequency Integrated Circuit Design
- Semiconductor materials and devices
- Photonic and Optical Devices
- Electromagnetic Compatibility and Noise Suppression
- Analog and Mixed-Signal Circuit Design
- Vibration Control and Rheological Fluids
- Semiconductor Lasers and Optical Devices
- Advancements in Semiconductor Devices and Circuit Design
- Effects of Vibration on Health
- Vehicle Dynamics and Control Systems
- Ferroelectric and Negative Capacitance Devices
- VLSI and Analog Circuit Testing
- Optical Network Technologies
- Microwave Engineering and Waveguides
- Ferroelectric and Piezoelectric Materials
- Advanced Algebra and Logic
- Electrostatic Discharge in Electronics
- Semiconductor materials and interfaces
- Engineering Applied Research
- Ergonomics and Musculoskeletal Disorders
- Turbomachinery Performance and Optimization
- Advanced MEMS and NEMS Technologies
- Dynamics and Control of Mechanical Systems
- Balance, Gait, and Falls Prevention
Samsung (South Korea)
2007-2024
Massachusetts Institute of Technology
2023
Sungkyunkwan University
2016-2018
Korea Advanced Institute of Science and Technology
2016
Chonnam National University
2011
Kyungpook National University
2007
Inha University
2005-2006
In this paper, an all-zero block detection scheme is proposed prior to DCT reduce the encoding complexity for high efficiency video coding (HEVC). Since many blocks tend have all zero coefficients after and quantization, it worthwhile detect all-zero-quantized input residual before so that subsequent transform quantization can be skipped. Unlike previous standards, HEVC adopts large sizes such as 16 × 8 8. It becomes more difficult accurately in because contains variety of content...
We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45 -nm CMOS process. Optimized dummy structures to remove components due pad routing metal are proposed. Parameters extracted proposed have excellent physical theoretical trends.
This paper proposes a 32.7 kHz self-biased wake-up timer using temperature-insensitive resistive current. A dual-loop structure with supply-regulation loop and frequency-locked determines the regulated voltages at both ends of temperature-compensated resistor cancels out amplifier offset voltages, thus generating current for switched capacitor. Moreover, self-biasing scheme in low-power design reduces power variation across temperature range eliminates necessity sub-μA reference generator....
A novel charge pump with adaptive body-bias compensation to minimise the current variation over a wide output voltage range is proposed. With 1.2 V supply voltage, proposed demonstrates constant of 140 µA across from 0.2 1.0 V. The less than 1.20 or 0.9% range, which helps keep loop bandwidth phase-locked (PLL) fixed and maximise dynamic range. Extremely low power bias circuits are provide at different levels. It believed that minimum among published results PLL pumps.
An electromagnetic synchronized switch damper integrated with the receding horizon optimal control law was developed to enhance damping characteristics of flexible beam structures subject dynamic loads. The system consists a magnet attached an aluminum and coil placed at bottom magnet. Both ends were connected external switching circuit, which includes transducer, capacitor, resistor, switcher designed for efficient energy dissipation reduce structural vibration. Further, coil-based...
This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock data recovery (CDR) circuit in 65-nm CMOS process. The deadzone-compensated frequency detector (DC-FD) the digital calibration of both bank control voltage voltage-controlled oscillators (VCOs) allow precise acquisition even with high input jitter. scheme extends supported rates, temperature compensation technique allows uninterrupted video transmission bit error rate (BER) below 10 <sup...
The conventional cellular mobile device needs a tens-of-MHz main crystal oscillator (XO) and 32.768kHz real-time clock (RTC) XO for RF ultra-low-jitter PLLs sleep operation, respectively. To minimize BoM cost PCB area by reducing the number of crystals, low-power with fractional divider (DIV.) in [1] is reported RTC. However, high-power-consuming start-up operation high-Q-factor inevitable. on-chip RC (RCO) can be an alternative to RTC due its compact excellent stability over process,...
This paper presents vibration control performance of a semi-active electrorheological (ER) seat suspension incorporating model the human body. A cylindrical type ER damper is manufactured and its field-dependent damping force experimentally evaluated. body derived integrated with governing equations an suspension, which consists seat, spring, damper. The seat-driver then reduced through balanced reduction in order to design state observer from each segment obtained for evaluation. skyhook...
We have successfully demonstrated a world smallest 0.25 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell 1T1C 64 Mb FRAM at 130 nm technology node. This small size was achieved by scaling down capacitor stack, using the following technologies: robust glue layer onto bottom electrode of capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and top-electrode-contact-free (TEC-free) scheme. The new is suitable for...
A radio-frequency equivalent circuit model for the symmetric vertical natural capacitor (VNCAP) in a 45 nm low-standby-power CMOS process is presented. The average effective capacitance density of 2.24 fF/ mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> obtained from VNCAPs 1 times (M1 - M5) + 2 (M6 M7) metal-layer configuration after open-short de-embedding procedure. proposed consists main series network and lossy substrate...
This paper proposes a ring-VCO-based fractional-N PLL with noise-power reconfigurable ring-VCO and self-chopped reference frequency doubler for multi-standard applications. To cover the various specifications of SoC chips, jitter power proposed can be through R C adjustments ring-VCO. Moreover, provides 6 dB improvements on DSM quantization noise without spurs. In addition, also guarantees wide range from 9.4 MHz to 2.4 GHz while maintaining optimum loop-bandwidth against process, voltage,...
Abstract In this paper, it is presented a capacitive touch sensor IC with noise‐based hybrid sensing scheme, which provides two modes noise detector. noiseless environment, fast power‐efficient peak‐detection mode enabled and if detected, the switched to high‐SNR demodulation mode. Therefore, adaptively offers both speed high immunity without large power consumption. The proposed shows higher than 50‐dB SNR in over 240‐Hz reporting rate 2.8‐mW analog consumption, evaluated 4‐inch AMOLED...
This paper proposes a fractional-N sub-sampling ring PLL employing jitter-tracking DLL-assisted DTC. The DTC achieves 0.49ps resolution and 0.98LSB <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> INL with dynamic range reduction through multi-phases of the DLL. In addition, an adaptive pulse-width control technique allows loop BW to be insensitive PVT, yielding <; 9.6% jitter variation. proposed fabricated in 14nm FinFET CMOS process...
A new method to extract substrate resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sub</sub> ) for small-sized nano-scale metal oxide semiconductor field effect transistors (MOSFETs) including bulk FinFETs is proposed and compared with conventional method. The R 's extracted from small-size MOSFETs by using the are shown have frequency independent characteristics, unlike those Proposed equivalent circuit explains well behavior body...
The substrate resistances of highly scaled bulk FinFETs were extracted by using a new RF equivalent circuit, and this approach was verified 3-D device simulator. Small signal model parameters through proposed circuit Y-parameter analysis. Unlike the conventional method, method showed frequency-independent in devices. extraction is investigated with number finger, geometry, bias condition. Our up to 50 GHz devices operating saturation region.
This paper presents a low power and area efficient wireless direct sampling receiver (DSR) implemented in 14nm FinFET process for frequency modulation (FM) receiver. By employing digital mixer channel selection, the inductor based local oscillator can be removed, I/Q matching requirements analog front-end are vastly relaxed. Implemented process, proposed FM-DSR with FPGA demodulation achieves 31 dB SNR -90 dBm sensitivity level 71 -47 input while consuming 11.74 mW.
This paper presents robust control performances of a semi-active electro-rheological (ER) seat suspension incorporating vibration model human-body. A cylindrical type ER damper is manufactured for commercial vehicle system and its field-dependent damping force experimentally evaluated. human-body then derived integrated with the governing equations system. The seat-driver featured by high order degree-of-freedom (DOF) reduced through balanced reduction to design controller. By imposing...
This paper presents an RF CMOS transceiver supporting all cellular protocols including 5G Frequency Range (FR) 1 with eighteen receiver pipelines and two chains of transmitters. To transfer data for combinations carrier aggregation (CA) a dual-band quad-GNSS system efficiently to modem, fully-digital interface is implemented instead conventional analog interface, resulting in enhanced signal integrity smaller PCB area. The digitally-intensive design this work, 14nm process, boosts the...
This work presents a 2.4-to-4.2GHz type-I ring-oscillator-based PLL with wide bandwidth. The switched-capacitor-bias ($\mathrm{I}_{\mathrm{S}\mathrm{C}}$)-based samphng PD ensures the PVT-robustness and high linearity across lock-in range. Due to its merits, effect of fast phaseerror correction (PEC) scheme is maximized so that integrated-jitter 440.2f$\mathrm{s}_{\mathrm{r}\mathrm{m}\mathrm{s}}$ 4. 3mW. Furthermore, optimal varactor (OV)-tuned RO shields ripple caused by sampling PEC,...
Since the bandwidth and clock frequency of a memory interface have been increased for 5G communication, its power consumption should be tightly managed to extend battery time. To improve energy efficiency, dynamic voltage scaling (DVFS) technique [1] that optimally adjusts operating depending on system scenarios has used so wide range is required. For example, advanced double data rate 5 (DDR5) mandates from 2.1 9.6 GHz. Therefore, ring oscillator (RO) based PLLs are commonly utilized in...
To satisfy the requirements of high-order modulations such as 256QAM in 5G RF transceivers, sampling phase-locked-loop (PLL) [1] is a promising solution ultra - low-jitter local oscillator. In type PLLs, design crystal oscillator key element to achieve low in-band phase noise (PN). Even though differential structure [2] or stacked amplifier [3] improves figures-of-merit (FoM) oscillators, absolute PNs at frequency offsets (f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This brief presents a 208-MHz, 0.75-mW self-calibrated reference frequency quadrupler (RFQ), which provides 4x higher clock with minimal deterministic error. The digital-assisted calibration technique is exploited to compensate wide range of and duty cycle errors reduce the noise degradation analog loop. Also, instead utilizing corrector for 2x clock, reusing delay cell reduces power consumption by 50%. fractional-N ring-PLL proposed RFQ was implemented in 4nm FinFET CMOS process. active...