A5078572020- Semiconductor materials and devices
- Advanced Memory and Neural Computing
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Integrated Circuits and Semiconductor Failure Analysis
- Phase-change materials and chalcogenides
- Chalcogenide Semiconductor Thin Films
- Electronic and Structural Properties of Oxides
- Quantum Dots Synthesis And Properties
- Low-power high-performance VLSI design
- Semiconductor materials and interfaces
- Transition Metal Oxide Nanomaterials
- Silicon Carbide Semiconductor Technologies
- Machine Learning and ELM
- CCD and CMOS Imaging Sensors
- Magnetic properties of thin films
- Neural dynamics and brain function
- Copper-based nanomaterials and applications
- Semiconductor Quantum Structures and Devices
- Nanowire Synthesis and Applications
- Neuroscience and Neural Engineering
- Silicon and Solar Cell Technologies
- GaN-based semiconductor devices and materials
- VLSI and Analog Circuit Testing
- Quantum and electron transport phenomena
CEA LETI
2015-2024
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2015-2024
Université Grenoble Alpes
2010-2024
CEA Grenoble
2011-2023
Institut polytechnique de Grenoble
2007-2021
Direction de la Recherche Technologique
2021
Centre National de la Recherche Scientifique
2021
Centre d’Élaboration de Matériaux et d’Études Structurales
2021
Université de Toulouse
2021
Samsung (South Korea)
2012-2021
This paper presents the current state of understanding factors that limit continued scaling Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis ways in which application-related considerations enter into determination these limits. The physical origins limits are primarily tunneling currents, leak through various barriers a MOS field-effect transistor (MOSFET) when it becomes very small, thermally generated subthreshold currents. dependence leakages on...
Recent changes in CMOS device structures and materials motivated by impending atomistic quantum-mechanical limitations have profoundly influenced the nature of delay power variability. Variations process, temperature, supply, wear-out, use history continue to strongly influence delay. The manner which tolerance is specified accommodated high-performance design dramatically as technologies scale beyond a 90-nm minimum lithographic linewidth. In this paper, predominant contributors variability...
To a large extent, scaling was not seriously challenged in the past. However, closer look reveals that early signs of limits were seen high-performance devices recent technology nodes. obtain projected performance gain 30% per generation, device designers have been forced to relax subthreshold leakage continuously from one several nA/µm for 250-nm node hundreds 65-nm node. Consequently, passive power density is now significant portion budget high-speed microprocessor. In this paper we...
Double-gate devices will enable the continuation of CMOS scaling after conventional has stalled. DGCMOS/FinFET technology offers a tactical solution to gate dielectric barrier and strategic path for silicon point where only atomic fluctuations halt further progress. The nature processes required fabricate these structures enabled rapid experimental progress in just few years. Fully integrated circuits have been demonstrated 180 nm foundry-compatible process, methods mapping conventional,...
Double gate devices based upon the FinFET architecture are fabricated, with lengths as small 30 nm. Particular attention is given to minimizing parasitic series resistance. Angled extension implants and selective silicon epitaxy investigated methods for resistance in FinFETs. Using these two techniques high performance fabricated on-currents comparable fully optimized bulk technologies. The influence of fin thickness on device short channel effects discussed detail. Devices fins oriented...
A survey of industry trends from the last two decades scaling for CMOS logic is examined in an attempt to extrapolate practical directions technology as lithography progresses toward point at which limited by size silicon atom itself. Some possible various specialized applications are explored, and it further conjectured that double-gate MOSFETs will prove be dominant device architecture this era scaling.
A simple but accurate expression for the effective drive current, I/sub eff/, CMOS inverter delay is obtained. We show that choice eff/=(I/sub H/+I/sub L/)/2, where L/=I/sub ds/(V/sub gs/=V/sub dd//2,V/sub ds/=V/sub dd/), and H/=I/sub dd/,V/sub dd//2) defined, accurately predicts when tested against compact models over a variety of conditions hardware results in 90 nm node technology. Furthermore, this definition eff/ captures behavior non-traditionally scaled devices, mobility V/sub...
Energy efficiency has become a ubiquitous design requirement for digital circuits. Aggressive supply-voltage scaling emerged as the most effective way to reduce energy use. In this work, we review circuit behavior at low voltages, specifically in subthreshold (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</inf> < V xmlns:xlink="http://www.w3.org/1999/xlink">th</inf> ) regime, and suggest new strategies energy-efficient design. We begin...
While Resistive RAM (RRAM) are seen as an alternative to NAND Flash, their variability and cycling understanding remain a major roadblock. Extensive characterizations of multi-kbits RRAM arrays during Forming, Set, Reset operations presented allowing the quantification intrinsic factors. As result, fundamental limits filament-based in full resistance range identified.
We demonstrate successful scalability of conventional 100μm diameter TiN/HZO/TiN capacitors down to 300nm by successfully co-integrating them for the first time in Back-End-Of-Line 130nm CMOS technology. Excellent performance are reported on those scaled bitcells, such as remnant polarization 2.PR > 40μC/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , endurance 10 xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> cycles, switching...
This paper presents an overview of emerging memory technologies. It begins with the presentation stand-alone and embedded technology evolution, since appearance Flash in 1980s. Then, progress technologies (based on filamentary, phase change, magnetic, ferroelectric mechanisms) is presented a review major demonstrations literature. The potential these for storage applications addressing various markets products discussed. Finally, we discuss how rise artificial intelligence bio-inspired...
Metal-gate FinFET and FDSOI devices were fabricated using total gate silicidation. Devices satisfy the following metal-gate technology requirements: ideal mobility, low leakage, high transconductance, competitive I/sub on//I/sub off/, adjustable V/sub t/. Six silicide materials are presented, as well two workfunction engineering methods.
In this paper, we present experimental evidence on the voltage-dependence of voltage acceleration factors observed ultrathin oxides from 5 nm down to /spl sim/1 over a wide range voltages sim/2 V 6 V. Two independent approaches, area scaling method and long-term stress, are used investigate phenomenon. We show exponential law with constant voltage-acceleration factor violates widely accepted fundamental breakdown property Poisson random statistics while voltage-dependent described by an...
Resistive random access memories (RRAMs) feature high-speed operations, low-power consumption, and nonvolatile retention, thus serving as a promising candidate for future memory applications. To explore the applications of RRAM, switching variability cycling endurance need to be addressed. This paper presents extensive characterizations multi-kb RRAM arrays during forming, set, reset, operations. The relationships among programming conditions, window, features are presented. experimental...
The brain performs intelligent tasks with extremely low energy consumption. This work takes its inspiration from two strategies used by the to achieve this efficiency: absence of separation between computing and memory functions reliance on low-precision computation. emergence resistive technologies indeed provides an opportunity tightly co-integrate logic in hardware. In parallel, recently proposed concept a Binarized Neural Network, where multiplications are replaced exclusive NOR (XNOR)...
Abstract Phase change memory can provide a remarkable artificial synapse for neuromorphic systems, as it features excellent reliability and be used an analog memory. However, this approach is complicated by the fact that crystallization amorphization differ radically: realized in very gradual manner, similarly to synaptic potentiation, while process tends abrupt, unlike depression. Addressing non‐biorealism of requires system‐level solutions have considerable energy cost or limit generality...
Limited endurance of resistive RAM (RRAM) is a major challenge for future computing systems. Using thorough tests that incorporate fine-grained read operations at the array level, we quantify first time temporary write failures (TWFs) caused by intrinsic RRAM cycle-to-cycle and cell-to-cell variations. We also permanent (PWFs) irreversible breakdown/dissolution conductive filament. show how technology-, programing-, system resilience-level solutions can be effectively combined to design new...
This paper describes the design, fabrication, and characterization of 0.1-µm-channel CMOS devices with dual n+/p+ polysilicon gates on 35-A gate oxide. A 2× performance gain over 2.5-V, 0.25-µm technology is achieved at a power supply voltage 1.5 V. In addition, 20× reduction in active power/circuit obtained < 1 V same delay as 0.25-micron CMOS. These results demonstrate feasibility high-performance low-power room-temperature 0.1-µm technology. Beyond 0.1 µm, number fundamental device issues...
Issues, challenges, and potential directions for further performance gains beyond 0.1 /spl mu/m CMOS are explored. Gate oxide thickness will soon be tunneling-current limited below 20 Aring/, or roughly 7 atomic layers. V/sub dd/ scaling slow to accommodate pressure on from t/-nonscaling, pushing higher electric fields. Highly abrupt, vertically laterally nonuniform SUPER-HALO doping profiles required control of short-channel effects in the 0.05 channel-length regime. More than 6-levels...
We present the status and direction of silicon semiconductor technologies targeted for applications such as wireless, networking, instrumentation, storage markets. Various technological aspects multiple branches RF foundry that are based on standard compatible CMOS node discussed - SiGe BiCMOS HP ("high performance") tailored to high-frequency applications, WL ("cost wireless/storage RF-CMOS optimized low-cost consumer applications. Future opportunities challenges advancement in described...
Abstract The impurity states occurring in CuInSe 2 crystals after annealing an atmosphere of Se and in‐diffusion In are determined by electrical measurements. experimental results suggest the conclusion that shallow donor with ionization energy about 10 meV is due to vacancies, acceptor 35 100 interstitials. deep 400 assumed be Fe 2+ substituted on sites.
RRAM-based in-Memory Computing is an exciting road for implementing highly energy efficient neural networks. This vision however challenged by RRAM variability, as the implementation of in-memory computing does not allow error correction. In this work, we fabricated and tested a differential HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based memory structure its associated sense circuitry, which are ideal computing. For first...
Abstract Here, the impact of copper and oxygen vacancy balance in filament composition as a key factor for oxide‐based conductive bridge random access memories (hybrid resistive (HRRAMs)) performances is investigated. To this aim, several RRAM technologies are studied using various layers top electrodes. Material analyses allow to highlight hybrid aspect HRRAM filament. Density functional theory simulations used extract microscopic features differences from material point view. Integrated...
Resistive random access memories (RRAM) are novel nonvolatile memory technologies, which can be embedded at the core of CMOS, and could ideal for in-memory implementation deep neural networks. A particularly exciting vision is using them implementing Binarized Neural Networks (BNNs), a class networks with highly reduced footprint. The challenge resistive memory, however, that they prone to device variation, lead bit errors. In this work we show BNNs tolerate these errors an outstanding...