A5019621140- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Photolithography Techniques
- Low-power high-performance VLSI design
- Ferroelectric and Negative Capacitance Devices
- Thin-Film Transistor Technologies
- Silicon and Solar Cell Technologies
- Silicon Carbide Semiconductor Technologies
- Copper Interconnects and Reliability
- 3D IC and TSV technologies
- Advanced Memory and Neural Computing
- VLSI and Analog Circuit Testing
- Semiconductor materials and interfaces
- Radiation Effects in Electronics
- Electronic Packaging and Soldering Technologies
- VLSI and FPGA Design Techniques
- Electronic and Structural Properties of Oxides
- Cardiac Imaging and Diagnostics
- Online Learning and Analytics
- Radio Frequency Integrated Circuit Design
- Intelligent Tutoring Systems and Adaptive Learning
- GaN-based semiconductor devices and materials
- Electrostatic Discharge in Electronics
- Computer Science and Engineering
Instituto Dante Pazzanese de Cardiologia
2024
Faculdade de Ciências Médicas da Santa Casa de São Paulo
2024
IBM (United States)
2012
Toshiba (United States)
2010-2011
Toshiba (Japan)
1998-2010
TU Wien
2007
Tohoku University
2003-2005
Toshiba (South Korea)
1987-2003
Sony Computer Science Laboratories
2002
The concept of future scaling-down for RF CMOS technology has been investigated in terms f/sub T/, max/, noise, linearity, and matching characteristics, based on simulation experiments. It found that gate width finger length are key parameters, especially sub-100 nm generations.
The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling both the logic blocks high-density SRAM cells from low power-dissipation viewpoint. For operation, they have estimated power speed inverter gates with a fanout=3. They find that optimum is very sensitive to switching activity in addition operation frequency. propose integrate two sets of transistors having different dd/s on chip. In portions chip high frequency or activity, use H which th/ are moderately...
Hot-carrier-induced degradation surface-channel (p/sup +/ polysilicon gate) and buried-channel (n/sup pMOSFETs is discussed. In the shallow gate bias region, a hot-carrier mode by drain avalanche hot hole injection was found for pMOSFETs. Trapped holes interface state generation, which were not observed in pMOSFETs, detected. this structure smaller than that structure. Three reasons are The deep-gate region also investigated. an interface-state generation without threshold-voltage shift both...
The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the degradation were analyzed using simple degraded MOSFET model. It was found number of generated interface states is defined uniquely by amount peak substrate current, independently from gate-oxide thickness. major cause in device mobility due to states. measured and formulated. explained difference between vertical electric field dependence Coulomb scattering term phonon under inversion...
In this paper, we present a cost-effective 28 nm CMOS technology for low power (LP) applications based on high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and, using the ARM Cortex-R4F as reference, achievement of an overall 2.4x area reduction in from 45 technology. Our high-density SRAM bit-cell (area= 0.120mm ) has demonstrated Static Noise...
High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si depletion the drive current by 8%. systematic study on process-induced performed it confirmed that new scheme such as eSiGe stress liner techniques suitable CMOSFET. It factors using multiple...
Gate density is ultimately increased to 2100 kGates/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> by pushing the critical design rules without increasing circuit margin in 45 nm technology. Layout dependences for stress enhanced MOSFET including contact positioning, 2nd neighboring poly effect, and bent diffusion are accurately modeled first time. With constructed flow, gate length change of −2.8% +3.6% Idsat −10% +14% removed from...
Performance improvement of CMOSFET by adopting <100>-channel direction with high tensile stress gate capping layer (GC liner-SiN) was demonstrated. For pMOSFET, higher hole mobility and lesser short channel effect (SCE) results in 20% I/sub on/. In addition, this not sensitive to local uniaxial strain. nMOSFET, similar <110>-channel, 10% on/ is realized layer. Thus, technology can improve the performance nMOSFET pMOSFET without introducing specific additional processes for pMOSFET.
In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm pitch & ULK dielectrics. Compared with 28nm technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X equivalent leakage is achieved through co-optimization of HKMG process engineering. A fully...
The long-term reliability for a p/sup +/ poly gate MOS structure under low electric field bias temperature (BT) stress is studied. A significant increase in interface-state density was observed such positive conditions. This phenomenon not the n/sup case. mechanism this investigated detail. Several possible causes, as mobile ions, excess boron concentration oxide, electron injection from substrate, impact ionization and hole electrode, were considered. All of except injection, obviated by...
Experiments have shown that the electromigration reliability for conventional nonfilled via holes decreases with hole diameter reduction. Tungsten-filled reliability, however, is independent of and improves significantly compared structure. The failure mechanism tungsten-filled structures was investigated by two-dimensional numerical simulation. Current crowding points were found near edge in aluminum part. Via resistance change during test also evaluated. When aluminum-silicon used metal...
An application that takes advantage of FeRAM characteristics is replacing current DRAM, which then becomes high-performance nonvolatile RAM cache. This improves system performance for many kinds computer systems, including mobile PCs, cellular phones, digital video products, and storage systems such as SSDs. However, the highest capacity in RAMs allow frequent cache reads writes limited to 64 Mb. The maximum read bandwidth 400 Mb/s write 200 memories reported date. FeRAm was demonstrated 4M...
A new low-resistivity poly-metal gate structure, W/WSiN/poly-Si, is proposed, uniform ultrathin (<1 nm) WSiN barrier layer was formed by annealing a W(100 nm)WN/sub x/(5 nm)/poly-Si structure. The W/WSiN/poly-Si structure found to be thermally stable even after at 800/spl deg/C. sheet resistivity of the nm)/WN/sub nm)/poly-Si(100 as low 1.5 /spl Omega//spl par//spl square/ and independent line-width from 0.52 mu/m 0.12 mu/m. this 40% lower than that nm)/TiN(5 In addition, an equivalent...
Concept of future scaling-down for RF CMOS has been investigated in terms fT, fmax, noise, linearity, and matching characteristics, based on simulation experiments. It found that gate width finger length are the key parameters especially sub-100 nm generations.
Channel width dependence of hot-carrier induced drain current degradation was investigated for nMOSFETs with optimized shallow trench isolation (STI) structure in which no MOS hump characteristics were observed. In an STI structure, increase the narrow channel region found first time. The stress time rate increases drastically below 0.5 /spl mu/m width. This phenomenon is caused by accelerated generation and higher hot-electron injection at adjacent to edge. lifetime would be seriously...
We present the state-of-the-art 45nm high performance bulk logic platform technology which utilizes, for first time in industry, ultra NA (1.07) immersion lithography to realize highly down-scaled chip size. Fully renovated MOSFET integration scheme features reversed extension and SD diffusion formation is established meet Vt roll-off requirement with excellent transistor of Ion=1100muA/mum nFET Ion=700muA/mum pFET at Ioff=100nA/mum. Also, we achieved BEOL reliability manufacturability by...
Ultra low power circuit operation is demonstrated with dopant segregated Schottky (DSS) source/drain transistors for the first time. DSS greatly improves propagation delay in multiple fan-in NAND gates at constant standby current. The enhanced to 21% 0.8V 3-input gates. Energy product (EDP) improved by more than 50%
Hot carrier degradation was studied for surface-channel (p/sup +/ polysilicon-gate) PMOSFETs in comparison with buried-channel (n/sup PMOSFETs. In the shallow gate bias region, a mode by drain avalanche hot-hole injection found Here, trapped holes and interface state generation, which were not observed PMOSFETs, detected. deep-gate-bias channel interface-state-generation without threshold voltage shift both types of studied.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We report a new N/PFET Gate Patterning Boundary Proximity layout dependent effect in high-k dielectric/Metal (HK/MG) MOSFETs which causes anomalous threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ) modulation for the first time. investigated mechanism by using special test structures and process optimizations to suppress this dependency. Finally, we achieved best over all optimization makes it possible dependency...
In this paper, a 65nm CMOS platform featuring low power transistors and high density SRAM (CMOS5L) is reported. It offers wide range of Vth lineup very gate leakage as 0.06A/cm/sup 2/ by optimization halo implantation oxidation process. Pulse nitridation applied to suppress variations. Obtained characteristics MOSFET places top class among devices High for CMOS5L with the cell size 0.495/spl mu/m/sup developed. We demonstrate highly stable operation 7Mb array. This has property less than...
For the first time, we demonstrate standard cell gate density of 3650 KGate/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and SRAM 0.124 mum for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45 technology node, which is unattainable dual (DE) or double patterning (DP) poly/SiON stack.
This paper demonstrates a 100 nm generation SOC technology (CMOS IV) for the first time. Three types of core devices are presented with optimized gate oxynitrides their stand-by power conditions. advanced logic process is compatible 0.18 /spl mu/m/sup 2/ trench capacitor DRAM and 1.25 6 transistor SRAM. Two kinds high V/sub dd/ can be prepared by triple oxide process. Moreover, mixed signal applications, Ta/sub 2/O/sub 5/ MIM capacitors introduced into Cu low-k interconnects.
It has been reported that the dynamic recovery of drain current (I/sub d/) takes place soon after stress applied on gate is removed during a MOSFET negative bias temperature instability (NBTI) experiment. This phenomenon makes it very difficult to estimate NBTI degradation I/sub d/ (/spl Delta/I/sub correctly. The paper presents new characterization method in which effect quantitatively taken into account /spl precisely.
The effect of stress memorization technique (SMT) in performance and power reduction is maximized by choosing the appropriate stressor with large change spike RTA. 30% mobility enhancement 60% gate leakage have been achieved simultaneously. Stress distribution channel region for SMT confirmed to be uniform, hence layout dependency minimized aggressively scaled CMOS dense pitch rule(190nm) 45nm technology node.
A guideline for n/sup /spl minus// fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, greatest reduction in substrate current directly leads to most reliable FOLD structure. The path modulation phenomenon due trapped charge at extension region dominates hot-carrier induced characteristics change conventional lightly doped drain (LDD) with side-wall spacer. This is minimized its higher controllability electrode than LDD region....