A5036427590- 2D Materials and Applications
- Graphene research and applications
- Advancements in Semiconductor Devices and Circuit Design
- Nanowire Synthesis and Applications
- Semiconductor materials and devices
- Carbon Nanotubes in Composites
- MXene and MAX Phase Materials
- Ferroelectric and Negative Capacitance Devices
- Metal-Organic Frameworks: Synthesis and Applications
- Polyoxometalates: Synthesis and Applications
- Aluminum Alloys Composites Properties
- Thin-Film Transistor Technologies
- Magnesium Alloys: Properties and Applications
- Photonic and Optical Devices
- Advanced Fiber Optic Sensors
- Advanced Nanomaterials in Catalysis
- Transition Metal Oxide Nanomaterials
- Electromagnetic wave absorption materials
- Catalytic Processes in Materials Science
- Advanced Fiber Laser Technologies
- GaN-based semiconductor devices and materials
- Advanced Memory and Neural Computing
- Optical Network Technologies
- Laser-Matter Interactions and Applications
- Mechanical and Optical Resonators
Kunshan Govisionox Optoelectronic (China)
2019-2025
Peking University
2008-2024
University of California, Santa Barbara
2024
University of Hong Kong
2022-2024
East China University of Technology
2024
Chinese University of Hong Kong
2024
Hong Kong Polytechnic University
2002-2023
Chinese Academy of Sciences
2004-2023
Kunming University of Science and Technology
2023
Czech Academy of Sciences, Institute of Physics
2023
Single-walled carbon nanotubes (CNTs) may enable the fabrication of integrated circuits smaller than 10 nanometers, but this would require scalable production dense and electronically pure semiconducting nanotube arrays on wafers. We developed a multiple dispersion sorting process that resulted in extremely high purity dimension-limited self-alignment (DLSA) procedure for preparing well-aligned CNT (within alignment 9 degrees) with tunable density 100 to 200 CNTs per micrometer 10-centimeter...
Cooler electrons for transistors The operating power of field-effect is constrained in part by the minimum change voltage needed to current output. This subthreshold swing (SS) limit caused hotter from a thermal electron source leaking over potential gate electrode. Qiu et al. show that graphene can act as Dirac creates narrower distribution energies. When coupled carbon nanotube channel, decrease SS would allow supply be decreased 0.7 0.5 volts. Science , this issue p. 387
Abstract Since Si‐based Moore's law is physically limited, 2D semiconductors are proposed as successors to continue shrinking the transistor size for more Moore electronics. However, limited by experimental technology bottlenecks, theoretical predicted superiorities of transistors over state‐of‐the‐art Si have been lacking concrete evidence a decade. In this review, recent exciting breakthroughs presented, including gate length miniaturization sub‐1 nm limit, electrode contact optimization...
Abstract Due to high carrier mobility and excellent air stability, emerging 2D semiconducting Bi 2 O Se is attracting much attention as a potential channel candidate for the next‐generation field effect transistor (FETs). Although fabricated bilayer (BL) few layers FETs exhibit large current on/off ratio (>10 6 ) near‐ideal subthreshold swing value (≈65 mV dec −1 ), performance limit of ultrashort FET obscure. Here ballistic upper sub 10 nm BL metal‐oxide‐semiconductor (MOSFETs) simulated...
Abstract The merging 2D semiconductor tellurene (2D Group‐VI tellurium) is a possible channel candidate for post‐silicon field‐effect transistor (FETs) due to its high carrier mobility, drive current, and excellent air stability. performance limits of sub‐5‐nm ML metal‐oxide‐semiconductor FETs (MOSFETs) are explored by employing exact ab initio quantum transport simulations. An optimized p‐type MOSFET meets both the (along armchair zigzag directions) low power direction) requirements...
Inspired by the recent achievements of two-dimensional (2D) sub-5 nm MoS2 field effect transistors (FETs), we use ab initio quantum-transport methods to simulate transport properties gate-length monolayer (ML) MOSFETs. We find that ML double-gated MOSFETs (DGFETs) with 1, 3, and 5 gate length fail meet on-state current requirements in International Technology Roadmap for Semiconductors (ITRS) high-performance (HP) devices. However, both n- p-DGFETs can address ITRS low-power (LP)...
High-density semiconducting aligned carbon nanotube (A-CNT) arrays have been demonstrated with wafer-scale preparation of materials and shown high performance in P-type field-effect transistors (FETs) great potential for applications future digital integrated circuits (ICs). However, high-performance N-type FETs (N-FETs) not yet implemented A-CNTs, making development complementary metal-oxide-semiconductor (CMOS) technology, a necessary component modern ICs, impossible. In this work, we...
In this paper, top-gate thin-film transistors (TFTs) of two stacked double-channel layers derived from atomic layer deposition in combination with the plasma-enhanced chemical vapor (PECVD) process were fabricated. The Hall measurement shows that mobility indium gallium oxide (IGO)/indium zinc (IGZO) active is 1.6 times more amorphous In-rich IGZO/IGZO due to superior carrier percolation conduction paths polycrystalline IGO layer. Furthermore, x-ray photoelectron spectroscopy analysis...
With the scaling limits of silicon-based MOS technology, critical and challenging issue is to explore more alternative materials improve performance devices. Two-dimensional (2D) semiconductor WSe2 with a proper band gap inherent stability under ambient conditions makes it potential channel material for realizing new generation field-effect transistors (FETs). In light low on-state current experimental sub-10 nm 2D MoS2 FETs, we limitation monolayer (ML) device by using accurate ab initio...
Single-walled carbon nanotubes (CNTs) have been considered as a promising semiconductor to construct transistors and integrated circuits in the future owing their ultrathin channel thickness ultrahigh injection velocity. Although 5 nm gate-length CNT field-effect transistor (FET) has already experimentally fabricated demonstrates excellent device performance, potential or constraint factors on performance not explored revealed. Based benchmark of between experimental simulated FETs, we use...
Abstract Aligned carbon nanotube (A‐CNT) films are expected to be an ideal channel material for constructing field‐effect transistors (FETs) that outperform conventional transistors, and multiple methods developed fabricate A‐CNT with high semiconducting purity, good alignment, density. However, the reported A‐CNTs‐based FETs almost all depletion‐mode suffer from poor subthreshold swing (SS). In this study, enhancement‐mode (E‐mode) based on fabricated by systematically optimizing...
High-electron-mobility group III–V compounds have been regarded as a promising successor to silicon in next-generation field-effect transistors (FETs). Gallium arsenide (GaAs) is an outstanding member of the family due its advantage both good n- and p-type device performance. Monolayer (ML) GaAs limit form ultrathin GaAs. Here, hydrogenated ML (GaAsH2) FET simulated by ab initio quantum-transport methods. The GaAsH2 metal–oxide–semiconductor FETs (MOSFETs) can well satisfy on-state current,...
Modern electronics demand transistors with extremely high performance and energy efficiency. Charge-based conventional semiconductors experience substantial heat dissipation because of carrier scattering. Here, we demonstrate low-loss topological phase change (TPCTs) based on tellurium, a Weyl semiconductor. By modulating the separation between Fermi level point tellurium through electrostatic gate modulation, device exhibits (Chern number ≠ 0) = semiconductors. In ON state, has transport...
Abstract Complementary metal‐oxide‐semiconductor (CMOS) field‐effect transistors (FETs) are the key component of a chip. Bulk indium arsenide (InAs) owns nearly 30 times higher electron mobility µ e than silicon but suffers from much lower hole h ( / = 80), thus unsuited to CMOS application with single material. Through accurate ab initio quantum‐transport simulations, performance gap between NMOS and PMOS is significantly narrowed predicted even vanished in sub‐2‐nm‐diameter gate‐all‐around...