A5067844511- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Neuroscience and Neural Engineering
- Physical Unclonable Functions (PUFs) and Hardware Security
- Ferroelectric and Negative Capacitance Devices
- Advancements in Semiconductor Devices and Circuit Design
- Security and Verification in Computing
- Potassium and Related Disorders
- Neural Networks and Reservoir Computing
- Advanced Data Storage Technologies
- Mechanical and Optical Resonators
- Neural dynamics and brain function
- Integrated Circuits and Semiconductor Failure Analysis
- Quantum and electron transport phenomena
- Magnetic properties of thin films
- CCD and CMOS Imaging Sensors
Korea Advanced Institute of Science and Technology
2019-2022
National NanoFab Center
2021
Yonsei University
2013
For the first time, a leaky integrate-and-fire (LIF) neuron with both excitatory and inhibitory characteristics is demonstrated using single MOSFET. No additional circuits such as comparator, reset circuit, or current-to-voltage converter well membrane capacitor are needed, thus LIF realized footprint of 6 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Because its gate terminal, firing selectively inhibited, which can improve energy...
Cointegration of single-transistor neurons and synapses for highly scalable neuromorphic hardware is demonstrated.
Abstract With the advance of internet things, numerous electronic devices are being connected to each other through internet. As number connections has increased, security become increasingly important. Physically unclonable function (PUF) is one essential approaches that can be used secure data in device. In this work, an independently controlled double‐gate (ICDG) transistor composed a poly‐crystalline silicon (poly‐Si) nanowire channel for PUF first demonstrated. Simply fabricated using...
A temperature sensor named a thermillator (thermo-oscillator) is demonstrated, consisting of single device with an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -emitter, p-base and -collector. The floating body shows inherent oscillation behavior. underlying mechanism the based on transistor latch (STL). Oscillation originates iterative charging discharging process in p-base, frequency ( <inline-formula...
An overturned charge injection synaptic transistor (OCIST) is experimentally demonstrated for neuromorphic hardware computing. The structure of the OCIST similar to that a conventional floating gate memory except directionality injection. valve layer (CVL) analogous blocking oxide device. employs CVL control flow gate, while utilizes tunneling as this. Because and are decoupled in OCIST, independently engineerable without any sacrifice quality scalability. Moreover, selection spectrum...
A highly scalable neuron composed of one biristor and two transistors (1B2T neuron) is proposed. The output voltage pulsewidth in the 1B2T are reduced compared with that previously reported (1B) solely. approach can greatly enhance energy efficiency neuromorphic hardware by decreasing consumption. To demonstrate neuron, SPICE simulations were performed, reflecting measured spiking property fabricated 1B. consumption analyzed under various conditions (2T) such as threshold applied voltage. In...
A steep-slope phenomenon is experimentally demonstrated and analyzed with a novel FET referred to as charge pump (CP-FET) by using transient switching of the floating gate voltage. It also analytically modeled verified simulation. The CP-FET, which very similar flash memory cell structure composed gate, was fabricated 100 % CMOS microfabrication. transition layer in CP-FET analogous blocking oxide device. Transient voltage achieved two factors. One capacitance mismatching between control...
Abstract A ternary logic decoder (TLD) is demonstrated with independently controlled double-gate (ICDG) silicon-nanowire (Si-NW) MOSFETs to confirm a feasibility of mixed radix system (MRS). The TLD essential component for realization the MRS. ICDG Si-NW MOSFET resolves limitations conventional multi-threshold voltage (multi- V th ) schemes required TLD. were fabricated and characterized. Afterwards, their electrical characteristics modeled fitted semi-empirically aid SILVACO ATLAS TCAD...
Self-heating effects (SHEs) were investigated through simulations for 3-D V-NAND flash memory. The SHEs are varied by adjusting the thickness of poly-crystalline channel, number stacked cells along with a bitline, and configuration multilevel cell. simulation data show that temperature change was smaller than 3 K under read operation; therefore, no longer concern advances in V- NAND memory technology. In addition, we whether influenced thermally isolated as novel architecture named...
Abstract Although SRAM is a well established type of volatile memory, data remanence has been observed at low temperature even for power-off state, and thus it vulnerable to physical cold boot attack. To address this, an ultra-fast sanitization method within 5 ns demonstrated with physics-based simulations avoidance the attack SRAM. Back-bias, which can control device parameters CMOS, such as threshold voltage leakage current, was utilized sanitization. It applicable temporary erasing...
Abstract Although SRAM is a well-established type of volatile memory, data remanence has been observed at low temperature even for power-off state, and thus it vulnerable to physical cold boot attack. To address this, an ultra-fast sanitization method within 5 ns demonstrated with physics-based simulations avoidance the attack SRAM. Back-bias, which can control device parameters CMOS, such as threshold voltage leakage current, was utilized sanitization. It applicable temporary erasing...
Abstract Co-integration of multi-state single transistor neurons and synapses was demonstrated for highly scalable neuromorphic hardware, using nanoscale complementary metal-oxide-semiconductor (CMOS) fabrication. The were integrated on the same plane with process because they have structure a field-effect (MOSFET) different functions such as homotype. By virtue 100% CMOS compatibility, it also realized to co-integrate additional circuits, current mirror inverter. Such co-integration can...