A5000375941- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- Particle Accelerators and Free-Electron Lasers
- Particle accelerators and beam dynamics
- Engineering and Test Systems
- Radiation Effects in Electronics
- Low-power high-performance VLSI design
- Physical Unclonable Functions (PUFs) and Hardware Security
- Gyrotron and Vacuum Electronics Research
- 3D IC and TSV technologies
- Embedded Systems Design Techniques
- Interconnection Networks and Systems
- VLSI and FPGA Design Techniques
- Healthcare Education and Workforce Issues
- Semiconductor materials and devices
- Education and Learning Interventions
- Photocathodes and Microchannel Plates
- Advancements in Semiconductor Devices and Circuit Design
- Software Testing and Debugging Techniques
- Advancements in Photolithography Techniques
- Cryptographic Implementations and Security
- Advanced X-ray Imaging Techniques
- Electrostatic Discharge in Electronics
- Technology and Data Analysis
- Parallel Computing and Optimization Techniques
Pohang Accelerator Laboratory
2006-2022
Pohang University of Science and Technology
2006-2022
Hanyang University
2010-2021
Samsung Medical Center
2018
Sungkyunkwan University
2018
Nambu University
2018
Inha University
2018
Yonsei University
2009
Tsinghua University
2008
Pohang TechnoPark (South Korea)
2006
Neural progenitor cells (NPs) have shown several promising benefits for the treatment of neurological disorders. To evaluate therapeutic potential human neural (hNPs) in amyotrophic lateral sclerosis (ALS), we transplanted hNPs or growth factor (GF)-expressing into central nervous system (CNS) mutant Cu/Zn superoxide dismutase (SOD1G93A) transgenic mice. The were engineered to express brain-derived neurotrophic (BDNF), insulin-like factor-1 (IGF-1), VEGF, neurotrophin-3 (NT-3), glial...
This paper presents a design-for-debug (DfD) technique for network-on-chip (NoC)-based system-on-chips (SoCs). We present test wrapper and, and debug interface unit. They enable data transfer between tester/debugger core-under-test (CUT) or -debug (CUD) through the available NoC to facilitate debug. also novel core supporting logic transaction- scan-based operations. The basic operations supported by our scheme include event processing, stop/run/single-step selective storage of information...
Pseudo-random number generators (PRNGs) are based on the algorithm that generates a sequence of numbers arranged randomly. Recently, random have been generated through reinforcement learning mechanism. This method characteristics select optimal behavior considering every possible status up to point episode closing secure randomness such numbers. The LSTM is used for long-term memory previous patterns and selection new in consideration patterns. In addition, feature vectors extracted from...
A new microcode-based BIST (built-in self test) circuitry for embedded memory components is proposed in this paper. The implements march algorithms which are slightly modified by adopting DOF (degree of freedom) concept to detect ADOFs (address decoder open faults) on top conventional stuck faults. Furthermore it shown that the can capture a few NPSFs (neighborhood pattern sensitive coupled with cellular automata address generator and patterns. lends itself performing different combinations...
The application diversity and evolution of AI accelerator architectures require innovative DFT solutions to address issues such as test time, power, performance area overhead. Full scan DFT, because its enhanced controllability observability, is an industrial de facto strategy. However, it may not yield optimal solution with stringent design constraints edge-based accelerators. In this paper, a novel architecture based on selective-partial proposed for performance, power (PPA) overhead...
For supporting real-time interaction in distributed virtual environments (DVEs), it is common to replicate world data at clients from the server. efficient replication, two schemes are used together general - prioritized transfer of objects and a caching prefetching technique. Existing approaches for DVEs exploit spatial relationship based on distances between user objects. However, fails determine which types more important an individual user, not reflecting user's interests. We propose...
This paper presents design-for-debug (DfD) methods for the reuse of network-on-chip (NoC) as a debug data path in an NoC-based system-on-chip (SoC). We propose on-chip core supporting logics which can support transaction-based debug. A interface unit is also presented to enable transfer through NoC between external debugger and core-under-debug (CUD). The proposed approach supports designs with multiple clock domains. It collection trace signatures facilitate long pattern sequences....
Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing highly integrated SoC. In this paper, an efficiently testable design technique introduced for SoC on/off-chip bus bridge on-chip advanced high-performance and off-chip peripheral-component-interconnect bus. The exploited by maximally reusing function achieve efficient functional structural...
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length number of feedback cycles are reduced with minimal switching activity variables. Experiment shows significant improvement dissipation for benchmark circuits.
A test interface controller (TIC) provided by ARM Ltd. is widely used for functional testing of system-on-a-chip (SoC) which adopts an advanced microcontroller bus architecture (AMBA) system. Unfortunately, this has the deficiency not being able to concurrently shift in and out structural scan patterns through TIC AMBA bus. This paper introduces a new based access mechanism (ATAM) speedy SoCs embedding cores. Since scan-in operations can be performed simultaneously, application time on...
The reconfigurable scan network standardized by IEEE std. 1687 offers flexibility in accessing the on-chip instruments, which significantly improves test cost. In this paper, we present a novel time-multiplexed 1687-network architecture that absolute application time of systems-on-chip at wafer-level as well package-levels tests. This leverages: 1) ever increasing tester channel frequency; 2) allowed frequencies two levels; and 3) offered 1687-network. We also test-time calculation method...
The Pohang Light Source (PLS) at the Accelerator Laboratory (PAL) is a third-generation light source, only synchrotron radiation facility in Korea, and fifth machine of its kind world (see Figure 1). In 1988, PAL was organized for construction PLS. Ground-breaking celebrated 1991, PLS completed 1994. 1995, opened two beamlines to public users. initially operated 2.0 GeV 1995. Since 2002, energy electron beam has been upgraded 2.5 Table 1 principal parameters PLS). Remarkable increases number...
Reusing on-chip functional interconnects as test access mechanism (TAM) appeared usual these days. One of the most important for highly crowded future system-on-chips (SoCs) is network-on-chip (NoC). Several NoC architectures including router and network interface (NI) have been proposed. They allow narrowcast multicast packets, in-order packet delivery, guaranteed throughput best-effort services. Exploiting preceding research, we present here a parallel method manipulated scheduling...
Multiple cell upsets (MCUs) become more and problematic as the size of technology reaches or goes below 65 nm.The percentage MCUs is reported significantly larger than that single (SCUs) in 20 nm technology.In SRAM DRAM, are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code interleaved data columns.However, content-addressable memory (CAM), column interleaving not practically possible.A novel error correction (ECC) scheme proposed this paper will cater...
Abstract The X-ray Free Electron Laser of Pohang Accelerator Laboratory (PAL-XFEL) was opened for the user in 2017. PAL-XFEL third XFEL facility world and well known small timing jitter FEL radiation. This success possible because significant achievements accelerator technology PAL-XFEL. They are not limited to a part but cover from injector electron beam generation undulator line In this review, we describe details newly developed devices that contributed successful construction
In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through IEEE-1149.1 TAP for scan delay test. By using only IEEE- 1149.1 pins as test-access and by embedding an on-chip test clock generator, low-cost automated equipment (ATE) can be efficiently utilized reduce testing costs. Experiments show effectiveness of our in utilizing ATE channels testing.
Today’s System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-tomarket requirements. However, the increasing cost of testing becomes a big burden in manufacturing highly integrated SoC. In this paper, an efficient parallel scan test technique introduced minimize application time. Multiple enable signals are adopted implement architecture achieve optimal time for patterns scheduled concurrent test. Experimental results show that times considerably reduced little area overhead.
Article Free AccessA new IEEE 1149.1 boundary scan design for the detection of delay defects Share on Authors: Sungju Park Dept. Computer Science & Engineering Hanyang University, SaDong, Ansan, Kyunggi-Do, 425-791 Korea KoreaView Profile , Taehyung Kim Authors Info Claims DATE '00: Proceedings conference Design, automation and test in EuropeJanuary 2000 Pages 458–462https://doi.org/10.1145/343647.343822Online:01 January 2000Publication History 13citation202DownloadsMetricsTotal...
Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, test schedulers are constrained with topological position cores and access points, which may negatively affect time. This paper presents a scalable hybrid data transportation scheme that allows simultaneously multiple heterogeneous NoC-based SoCs, while reusing NoC TAM. proposed scheme, single stimuli set CUTs is embedded into each flit packets those multicast targeted...