A5035493651- Analog and Mixed-Signal Circuit Design
- Particle Detector Development and Performance
- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- CCD and CMOS Imaging Sensors
- Advanced Memory and Neural Computing
- Radiation Detection and Scintillator Technologies
- Ferroelectric and Negative Capacitance Devices
- Radio Frequency Integrated Circuit Design
- VLSI and FPGA Design Techniques
- Semiconductor materials and devices
- Particle physics theoretical and experimental studies
- Atomic and Subatomic Physics Research
- Superconducting and THz Device Technology
- Diamond and Carbon-based Materials Research
- High-Velocity Impact and Material Behavior
- Physics of Superconductivity and Magnetism
- Numerical Methods and Algorithms
- Superconducting Materials and Applications
- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Sensor Technology and Measurement Systems
- Electrostatic Discharge in Electronics
- IoT-based Smart Home Systems
- Manufacturing Process and Optimization
Intel (India)
2022-2024
University of Petroleum and Energy Studies
2024
Indian Institute of Technology Roorkee
2021-2022
Indian Institute of Technology Mandi
2015-2021
Texas Tech University
2015-2019
Schlumberger (Norway)
2019
Indian Institute of Technology Indore
2015
Lawrence Berkeley National Laboratory
1990-2002
University of California, Berkeley
1990-2002
Princeton University
1992
The dark current properties of In/sub x/Ga/sub 1-x/As photodiodes, where x is varied from 0.53 to 0.82 for extending the long wavelength cutoff 1.7 2.6 mu m, are described. Detailed analyses optoelectrical parameters 0.82/Ga/sub 0.1/As photodiodes presented. Dark current, which a critical parameter and limits operation photodiode, analyzed compared with experimental values. Typical characteristics wavelengths m (x=0.53), 2.2 (x=0.72), (x=0.82) typical best values currents obtained...
Glass breaking in compartment fires is an important practical problem since a window acts as wall before and vent after breaking. If sufficient excess pyrolyzates have accumulated the hot layer, this sudden geometric change can lead to back draft flashover. As Emmons explained at first Symposium, windows break due thermal stress from differential heating of central portion shaded edge. The focus paper on quantifying connection between fire glass temperature predict time. tb. Techniques are...
An energy-efficient and multi-bit (4b) current-based analog compute in-memory (CIM) architecture is proposed in this paper. In CIM schemes, multiplication and-accumulate (MAC) operation performed on bitline, resultant output equivalent to bitline voltage drop <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\Delta \mathbf{V}_{\text{RBL}})$</tex> . However, dependence of xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta...
In this work, we propose an energy-efficient 64$\times $ 64 compute-in-memory (CIM) SRAM macro using a 7T bit-cell in 65nm CMOS UMC PDK. It supports 4-bit inputs, weights & outputs and performs MAC operations. also multiple row activations performing 1024 4b$\times $4b multiply accumulate (MAC) operations one clock cycle. Inputs are realized by the number of pulses on read wordline (RWL), which discharges bitline (RBL) according to bitwise multiplication inputs. Outputs 4 columns storing...
A symbolic analysis is presented to study a gain-boosted telescopic operational transconductance amplifier (OTA) with cross-coupled capacitor (positive feedback) across an auxiliary op-amp. The effects of positive feedback (PFC) on the pole–zero doublet introduced by op-amp are explored using analytical techniques and simulations. complete transfer function OTA PFC derived verified through circuit results obtained from simulation modelled show good agreement each other. Furthermore,...
In this brief, we present an energy-efficient and high compute signal-to-noise ratio (CSNR) XNOR accumulation (XAC) scheme for binary neural networks (BNNs). Transmission gates achieve a large signal margin (CSM) CSNR accurate XAC operation. The 10T1C SRAM bit-cell performs the in-memory operation without pre-charging larger bitline capacitances significantly reducing energy consumption per validation of proposed is done through post-layout simulations in 65nm CMOS technology with...
This paper presents the design of a fully differential low pass G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -C filter including preamplifier circuit as an input stage. The is targeted for biomedical application such electroencephalogram signal detection. complete supporting circuitry has been designed and implemented in standard 180 nm CMOS technology with supply voltage 1.8 V. post-layout simulation results show 21.8 dB closed...
This paper presents the first pixel detector realized using BCD8 technology of STMicroelectronics. The is a 160 nm process with bipolar, CMOS and DMOS devices; mainly targeted for an automotive application. silicon particle as sensor diode dimension 250 × 50 μm2. To support signal sensitivity diode, circuit simulations have been performed substrate voltage V. analog processing circuitry digital operation designed supply 1.8 Moreover, part confined in unit (diode sensor) to achieve 100 % fill...
This paper presents the design of a charge sensitive amplifier (CSA) for an analog processing circuit 47 × 6 silicon pixel detector array. The has been implemented in BCD 180 nm technology. A diode with area 250 50 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is used to realize unit sensor pixel. 100 % fill factor achieved by confining diode. Low power and efficient single ended folded cascode employed as basic building block CSA....
A low-power, sparse-scan, readout architecture has been developed for the ATLAS pixel front-end electronics. The supports a dual discriminator and extracts time over threshold (TOT) information along with 2-D spatial address of hits associates them unique 7-bit beam crossing number. IC implements level-1 trigger filtering event building (grouping together all in crossing) end column (EOC) buffer. events are transmitted 40 MHz serial data link protocol supporting buffer overflow handling by...
An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity imposed on capacitive DAC; replacing capacitor bank with only a one circuit. The regulated dynamic current mirror (RDCM) design introduced provide stabilized current. This invariable from RDCM, charging or discharging the circuit controlled by pulse width modulated signal realize switch DAC....
Inherent suppression of short channel effects, reduced sub-threshold and gate-dielectric leakage, good scalability ease integration in analog, digital RF circuits makes SOI Fin FET an important device for mixed signal system on chip (SoC) solutions. In this work, we carry out the feasibility study transistor analog to converter (ADC) design. This paper, first time, presents 8 bit, single switch-capacitor DAC SAR ADC design 45 nm double gate technology benchmarks simulation results with...
This paper presents four novel circuits for 7-bit Binary to BCD conversion. The first and second designs are modification of 3-3-1[1] algorithm with building blocks, which makes it area delay efficient in comparison previous design. third circuit is the implementation shift-add that this design compare existing architectures. final architecture presented algorithm, we called Range Detection Algorithm paper. power Simulation results specify these Shift-add area-efficient power-efficient as...
A symbolic analysis is presented to investigate the effect of cross coupled capacitor on a cascode operational amplifier. complete transfer function amplifier with derived and verified through circuit simulations. The modeled shows presence pole-zero doublet in amplifier's frequency response when cross-coupled connected across it. further results closed form equations optimize based user defined specifications such as, an open loop dc gain, unity gain bandwidth phase margin. To check...
The analog front-end of pixel readout electronics with dual threshold discriminator scheme has been measured extensively to determine the optimum performance and limitations circuit. preamplifier shows a peaking time 20 ns without capacitive load, which degrades only 30 load 350 fF. LEVEL-discriminator an adjustable in range 2000 6000e/sup -/ variable separation TIME-discriminator 800 1600e/sup -/. circuit allows full suppression out-of-time signals under conditions fF total power...
In this paper, the CDM logic style has been analyzed and compared with Conventional CMOS (C-CMOS) FinFET devices in super-threshold operation. Standard cell library gates C-CMOS developed various selected technologies (7nm, 10nm, 14nm, 16nm & 20nm) used to synthesize ISCAS'85 benchmark designs evaluate performance improvement. Synopsys silicon smart compiler tool generate standard libraries using device models from PTM design libraries. The Simulation results shows that based achieve average...