A5040423592- Photonic and Optical Devices
- Semiconductor materials and devices
- Semiconductor materials and interfaces
- Advancements in Semiconductor Devices and Circuit Design
- Nanowire Synthesis and Applications
- Silicon and Solar Cell Technologies
- Semiconductor Quantum Structures and Devices
- Semiconductor Lasers and Optical Devices
- Advanced Photonic Communication Systems
- Silicon Nanostructures and Photoluminescence
- Integrated Circuits and Semiconductor Failure Analysis
- Thin-Film Transistor Technologies
- Advanced Semiconductor Detectors and Materials
- Mechanical and Optical Resonators
- Phase-change materials and chalcogenides
- Transition Metal Oxide Nanomaterials
- Electrodeposition and Electroless Coatings
- Intermetallics and Advanced Alloy Properties
- Advanced Surface Polishing Techniques
- Rare-earth and actinide compounds
Ghent University
2018
KU Leuven
2013-2018
IMEC
2013-2018
Shizuoka University
2018
Birla Institute of Technology and Science, Pilani - Goa Campus
2017
University of California, Berkeley
2017
Indian Institute of Information Technology Design and Manufacturing Jabalpur
2017
Berkeley College
2017
Northwestern University
2017
University of Calabria
2017
We report the electrical properties of 60° dislocations originating from +1.2% lattice mismatch between an unintentionally doped, 315 nm thick Ge0.922Sn0.078 layer (58% relaxed) and underlying Ge substrate, using deep level transient spectroscopy. The are found to be split into Shockley partials, binding a stacking fault. exhibit band-like distribution electronic states in bandgap, with highest occupied defect state at ∼EV + 0.15 eV, indicating no interaction point defects dislocation's...
An imperative factor in adapting GeSn as the channel material CMOS technology, is gate-oxide stack. The performance of transistors degraded due to high density traps at oxide-semiconductor interface. Several oxide-gate stacks have been pursued, and a midgap Dit obtained using ac conductance method, found literature. However, detailed signature oxide like capture cross-section, donor/acceptor behavior profile bandgap, not yet available. We investigate transition region between stoichiometric...
The stringent device performance specifications of advanced scaled down technologies necessitates the implementation high mobility substrates such as SiGe, Strained Si (sSi), Ge, sGe and/or III-V materials like GaAs, InGaAs. control stress-induced defects remains a key challenge. Simple structures capacitors, diodes and transistors are used to assess electrical activity extended (dislocations; antiphase boundaries; ...) in high-mobility channel materials. Beside junction current analyses...
The low-frequency noise of n-channel InGaAs MOSFETs with Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric has been studied to assess the impact a S-passivation treatment on border trap (BT) density. It is shown that spectra are predominantly \(1/f\) -like, while normalized power spectral density (PSD) behaves according number fluctuations theory. BT derived from...
Deep levels associated with extended and point defects in MOS capacitors fabricated on unintentionally doped GeSn epitaxial layers Ge-on-Si substrates have been studied by Level Transient Spectroscopy (DLTS). A 9nm layer of Al 2 O 3 is deposited as high-k gate dielectric Molecular Beam Epitaxy. The trap kinetics origin defect states discussed. Also, it shown that the dislocation cores relaxed p-Ge are band-like donor-like lower half forbidden band gap, act carrier trapping recombination...
The electrical activity of extended defects (dislocations; antiphase boundaries;...) in high-mobility channel materials (strained-Si; (strained)-Ge, GaAs and InGaAs) is investigated by means simple device structures (p-n diodes MOS capacitors). These are fabricated substrates with a well-controlled density predominant defects, enabling the determination specific leakage current contribution per defect. It shown that there linear relationship between area threading dislocation for wide range...
Peculiar features of the deep level transient spectroscopy (DLTS) measurements on p+−i−n+ In0.53Ga0.47As tunnel diodes are explained. It is shown that due to high doping and large band tunneling conductance under reverse bias, DLTS spectrum prone erroneous interpretations. We discuss a procedure identify cause. In diodes, donor-like hole trap (H1) associated with point defect, an activation energy EV + 0.09 eV capture cross-section (2.4 ± 1) × 10−19 cm2, identified. addition thermal...
I-V characteristics of pGeSn/nGe diodes have been measured and show very interesting properties. Simulations the same structure are able to reproduce most observed behavior point predominant influence parameters such as band gap energy GeSn layer. C-V showing little frequency dependence also measured, their analysis for determination carrier concentration is confirmed by simulations. More investigations effect temperature, other features in defects at interface or bulk either layers, still...
GeSn has emerged as an interesting channel material for beyond 14 nm node devices, in CMOS well TFET configurations [1-3]. However, the advantages of sub-60mV/decade subthreshold swing (SS) due to increased band tunneling small direct-bandgap tensile-strained and higher carrier mobilities are dwarfed by presence traps gate stack. For Al or Hf based high-k dielectrics have been recognized candidates advanced stacks [4-6], where interlayer oxide (IL) shown decrease interface state density, Dit...
Electrically active defects in silicon-based epitaxial layers on silicon substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). Several aspects investigated, like, the impact of pre-epi cleaning conditions and effect a post-deposition anneal deep-level properties. It is shown that pre-cleaning thermal budget has strong influence at substrate/epi layer interface. At same time, Forming Gas Anneal can passivate to large extent defect states. Finally, it application increases...
a also at E.E. Dept. KU Leuven, Kasteelpark Arenberg 10, B-3001 Belgium Since the 45 nm CMOS node, high-k gate dielectrics and strain engineering go hand in to further boost transistor performance. An example of so-called global platform relies on thin strained-silicon (sSi) layer top strain-relaxed Si 1-x Ge x buffer (SRB) (Fig. 1). In addition, replacing thermally grown SiO 2 by deposited dielectric opens door for implementation high-mobility channel materials (Ge – pMOS; Ga As nMOS;...),...
Abstract not Available.
Metal nanostructures are one of the most significant components nanotechnology due to their physical and chemical properties like catalytic activity electron transport that allow them suitable for nano device fabrication. Moreover, anisotropic metallic importance in optical, diagnostic therapeutic applications. A large variety bottom-up methods techniques involving templates or capping agents have been used during last decade synthesize many types nanoparticles/structures. Electro deposition...
Defects in Ge0.947Sn0.053 layers grown using molecular beam epitaxy on (001) Si substrates with 4.9% mismatch are investigated optical, scanning, and transmission electron atomic force microscopies. It is shown that the strain relaxation occurs via introduction of 90° misfit dislocations short length, at Ge0.947Sn0.053/Si interface. An irregular morphology form mounds observed surface epitaxial Ge1−xSnx (0.031 ≤ x 0.093) found to be associated carbon impurities hetero-interface. A low-cost...