The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> and threshold voltage V xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> are evaluated under both static dynamic (i.e., switching) operating conditions. found to exhibit different dependence on the drive...

The drain induced dynamic threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\textrm {th}}$ </tex-math></inline-formula> ) shift of a notation="LaTeX">${p}$ -GaN gate HEMT with Schottky contact is investigated, and the underlying mechanisms are explained charge storage model. When device experiences high bias {DSQ}}$ , gate-to-drain capacitance notation="LaTeX">${C}_{\textrm {GD}}$...

Compared with the state-of-the-art Si-based power devices, enhancement-mode Gallium Nitride (E-mode GaN) transistors have better figures of merit and exhibit great potential in enabling higher switching frequency, efficiency, density for converters. The bridge-leg configuration circuit, consisting a controlling switch synchronous switch, is critical component many However, owing to low threshold voltage fast speed, E-mode GaN devices are more prone false turn-on phenomenon configuration,...

The impacts of static and dynamic gate stress on the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> ) instability in Schottky-type notation="LaTeX">${p}$ -GaN AlGaN/GaN heterojunction field-effect transistors are experimentally investigated. shifts negatively under large positive bias {G}}\_ {\text {stress}} &gt; 5$ V) by adopting...

By employing an interface protection technique to overcome the degradation of etched GaN surface in high-temperature process, highly reliable LPCVD-SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> gate dielectric was successfully integrated with recessed-gate structure achieve high-performance enhancement-mode (V xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ~ +2.37 V @ I xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = 100...

A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming second channel at interface between AlN-ISL underlying GaN. With gate recess terminated upper channel, operation was obtained with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML"...

GaN-based digital integrated circuits (ICs) are realized on a 6-inch GaN-on-Si power high-electron-mobility transistor (HEMT) platform by monolithic integration of enhancement/depletion-mode HEMTs using 0.5-μm gate technology. A direct-coupled FET logic inverter and 101-stage ring oscillator fabricated characterized. The exhibits large input voltage swing, wide noise margin, high temperature stability, while the features small propagation delay 0.1 ns/stage under supply 4 V. These ICs can...

The planar nature of the GaN heterojunction devices provides extended dimensions for implementing monolithic power integrated circuits. This article presents a comprehensive review advancements in integration. Basic building blocks integration platform based on p-GaN gate HEMT technology are discussed, including high- and low-voltage transistors, lateral field-effect rectifiers, resistors, capacitors. Exemplary designs driving circuit detection/protection circuits this demonstrated....

An AlGaN/GaN double-channel Schottky barrier diode (DC-SBD) with dual-recess gated anode is demonstrated in this letter. The DC-SBD features two recess steps. deep one cuts through channels, and the metal contacts 2DEG directly from sidewall of recessed heterostructure. shallow terminates at upper channel layer located adjacent to contact. A MOS field plate placed on region pinchoff underlying so off-state leakage current can be suppressed. Since lower separated etched surface, field-effect...

Developing effective technique to protect the etched-GaN surface from degradation in a high-temperature (i.e., at ~ 780°C) process, such as low-pressure chemical vapor deposition (LPCVD), is essential for fabricating normally-off GaN MIS-FETs with high-quality dielectric/GaN interface and highly reliable gate dielectric. In this letter, we developed an approach of obtaining protection layer using oxygen-plasma treatment followed by situ annealing prior LPCVD-SiN <sub...

An enhancement-mode GaN power switch with monolithically integrated gate driver is demonstrated on a 650-V GaN-on-Si device platform. The GaN-based features advanced designs such as bootstrapped gate-charging current source that enables high driving capability during the entire turn-on process and rail-to-rail output. transistor was characterized up to 300 V/15 A switching operations using double pulse tester, exhibits suppressed ringing fast speed. peak drain voltage slew rate d V/dt above...

An enhancement-mode GaN double-channel MOS-HEMT (DC-MOS-HEMT) was fabricated on a heterostructure, which features 1.5-nm AlN layer (AlN-ISL) inserted 6 nm below the conventional barrier/GaN hetero-interface, forming lower channel at interface between AlN-ISL and underlying GaN. With gate recess terminated upper layer, positive threshold voltage is obtained, while retains its high 2DEG mobility as heterojunction preserved. The device delivers small on-resistance, large current, breakdown...

GaN power ICs provide an elegant solution for high-frequency switching applications. This paper will first discuss the integration platform, which requires not only a high-voltage switch, but also peripheral low-voltage transistors, diodes, resistors, capacitors, etc. The components are preferably fabricated using same process steps of switch to be cost-effective. As example IC, integrated gate driving circuit is demonstrated. By adopting charge pump unit, novel driver in this work enables...

GaN power IC's are expected to help unlock the full potential of electronics, especially in terms promoting high-frequency switching applications. This paper first discusses a integration technology platform based on commercially available p-GaN gate HEMT technology. An integrated driver is presented as an example IC with enhanced performance, which bootstrap unit adopted realize rail-to-rail output voltage and fast speed. To deal GaN-specific design issues such unique dynamic V <sub...

Abstract Various 2D/3D heterostructures can be created by harnessing the advantages of both layered two-dimensional semiconductors and bulk materials. A semiconducting gate field-effect transistor (SG-FET) structure based on is proposed here. The SG-FET demonstrated an AlGaN/GaN high-electron mobility (HEMT) adopting single-layer MoS 2 as electrode. effectively turn off HEMT without sacrificing subthreshold swing breakdown voltage. Most importantly, deliver inherent over-voltage protection...

Using remote N2 plasma treatment to promote dielectric deposition on the dangling-bond free MoS2 is explored for first time. The induced damages are systematically studied by defect-sensitive acoustic-phonon Raman of single-layer MoS2, with samples undergoing O2 as a comparison. causes defects in mainly oxidizing along already defective sites (most likely flake edges), which results layer oxidation MoS2. In contrast, straining and mechanically distorting layers first. Owing relatively strong...

Dynamic ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of 650-V GaN-on-Si lateral power devices with a floating Si-substrate termination is investigated. Compared the grounded substrate termination, could deliver smaller dynamic R under higher drain bias (> 400 V) switching operation, but leads to larger low-drain (<; V). The underlying physical mechanisms are explained by tradeoff between charge storage in Si and...

The p-GaN gate capacitors with a metal/p-GaN/AlGaN/GaN structure are demonstrated on an enhancement-mode (E-mode) GaN-on-Si power device platform. High capacitance density of >170 nF/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is obtained operating voltage range 0 ~ 7 V. Frequency response the circular and interdigitated layout design characterized. It found that can suppress distribution effect reduce equivalent series...

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression plate deployed the etched upper GaN channel layer after barrier fully recess process, leading low OFF-state current of -20 nA/mm (at -100 V). drain metal adjacent plate, contacting MOS-channel and lower heterojunction from sidewall. A metal-2DEG Schottky contact with turn-ON voltage 0.5 V achieved....

The OFF-state drain leakage characteristics in 600-V p-GaN HEMTs with an ohmic gate contact are investigated under dynamic switching conditions instead of commonly used quasi-static measurement setup. It is found that fast current (dynamic I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) substantially higher than the slow-ramping due to weaker trapping effect buffer layer. With sufficiently large positive ON-state bias, further...

A three-terminal normally-off GaN switching device with highly desired low-loss reverse conduction capability was demonstrated using a chip-area-efficient structure design. This features interdigitated MIS-HEMT and high-performance embedded anti-parallel Schottky barrier diode (SBD) along the gate width direction, transistor sections sharing common ohmic contacts access regions. The MIS-HEMT/SBD ratio of 2:1 exhibits threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance interconnections. In this article, we demonstrate a GaN-based gate driver an overcurrent (OC) protection circuit and undervoltage lockout (UVLO) on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> -GaN HEMT platform. features rail-to-rail output voltage, suppressed ringing, tunable...

In this work, a new desaturation-based over-current protection circuit is proposed and monolithically integrated with GaN power HEMTs. Compared to traditional desaturation techniques, design features separated sensing branch blanking time controller. Such separation allows immediate of (OC) event, while the can be modified without considering speed. To mimic real situations in applications, was systematically characterized under different operating conditions. It deliver an accurate OC...

In this paper, static and dynamic performances of an AlGaN/GaN-on-Si power FET utilizing the integrated photonic-ohmic drain (PODFET) were systematically investigated. The operational mechanisms PODFET, including both conditions photon generation related physical processes, explained. switching tests carried out under two types hard conditions. With channel current inherently switched ON OFF in synchronization, PODFET can be significantly enhanced owing to pumping deep electron traps....