A5079131581- Analog and Mixed-Signal Circuit Design
- Particle Detector Development and Performance
- CCD and CMOS Imaging Sensors
- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Radiation Detection and Scintillator Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Particle physics theoretical and experimental studies
- Radiation Effects in Electronics
- Low-power high-performance VLSI design
- Energy Harvesting in Wireless Networks
- Microwave Imaging and Scattering Analysis
- Wireless Power Transfer Systems
- Semiconductor materials and devices
- Plasma Diagnostics and Applications
- Innovative Energy Harvesting Technologies
- Spectroscopy and Laser Applications
- Wireless Body Area Networks
- Human Mobility and Location-Based Analysis
- Analytical Chemistry and Sensors
- Advanced Power Amplifier Design
- Advanced Thermoelectric Materials and Devices
- Digital Filter Design and Implementation
- Biomedical and Engineering Education
- Advanced MIMO Systems Optimization
Hospital Universitário da Universidade de São Paulo
2021-2024
Universidade Federal de Minas Gerais
2019-2022
Universidade de São Paulo
2008-2020
Universidade Federal de Mato Grosso
2017
Industrial University of Santander
2016
Association of the Technological Integrated Systems Laboratory
2012-2014
The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in framework of EIC collider project, to equip trackers EPIC experiment. It designed be versatile, order adapted other usages like TPC, or photon detectors. integrates frontend block and an ADC each 64 channels, associated configurable digital DSP processor meant correct data reduce raw flux, limit output bandwidth. will compatible with continuous DAQ, but also able work triggered environment. Several...
This paper presents the test results of second prototype SAMPA, ASIC designed for upgrade read-out front end electronics ALICE Time Projection Chamber (TPC) and Muon (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply provides 32 channels, selectable input polarity, three possible combinations shaping time sensitivity. Each channel consists Charge Sensitive Amplifier, semi-Gaussian shaper 10-bit ADC; Digital Signal Processor digital filtering compression...
This paper presents the SAMPA, an ASIC designed for upgrade of read-out front end electronics ALICE Time Projection Chamber (TPC) and Muon Chambers (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply includes 32 channels, selectable input polarity, five possible combinations shaping time sensitivity. Each channel comprises Charge Sensitive Amplifier, semi-Gaussian shaper 10-bit ADC, followed by Digital Signal Processor. A prototype multi project run was...
Conseil Européen pour la Recherche Nucléaire is currently undergoing a major upgrade within the A Large Ion Collider Experiment (ALICE) detectors, one of four main experiments at Hadron (LHC) accelerator. The LHC luminosity will increase making heavy ions collision rate rise from 500 Hz to 50 kHz. Both time projection chamber (TPC) and muon (MCH) detectors demand new faster readout electronics, which support continuous cope with this higher rate. This paper presents serialized analog-digital...
This work presents a broadband RF rectifier for Wireless Power Transfer applications. The proposed circuit is based on voltage doubling configuration of SMS7630 packaged diodes, and new impedance matching approach composed microstrip transmission line an SMD inductor, which enables energy harvesting over wide frequency range with low device area. Experimental measurement demonstrated efficiency greater than 50% bandwidth 92% (0.68 - 1.84 GHz) 0 dBm input power 1.5 kΩ load, maximum 67.6% at...
In this paper a complete implementation and design of fully-synthesized 32-bit microcontroller in 130nm CMOS technology is presented. This the first featuring open source RISC-V instruction set all mounted through AXI4-Lite APB buses for communication process. The contains 10-bit SAR ADC, 12-bit DAC, an 8-bit GPIO module, 4kB-RAM, SPI AXI slave interface output verification, checking correct behavioral bridge. All peripherals are controlled by master that used programming device data flowing...
Abstract The upgrade of the ALICE TPC will allow experiment to cope with high interaction rates foreseen for forthcoming Run 3 and 4 at CERN LHC. In this article, we describe design new readout chambers front-end electronics, which are driven by goals experiment. Gas Electron Multiplier (GEM) detectors arranged in stacks containing four GEMs each, continuous electronics based on SAMPA chip, an development, replacing previous elements. construction these elements, together their associated...
This work presents the design and experimental results of a current mode Scalable Low-Voltage Signaling (SLVS) transceiver in 130 nm CMOS technology. The proposed transmitter includes feedback control which reduces common-mode voltage variations terms Vds bias transistor, an enable/disable operation mode, minimizes power consumption when data transmission is not requested. A rail-to-rail comparator topology was used to receiver circuit being robust transient with low high speed. DC 4.6 mW at...
A noise improved Charge Sensitive Amplifier (CSA) topology for a gaseous detector readout front-ends is presented. The proposed based on the traditional cascode with addition of PMOS to partially cancel channel thermal and flicker CSA input transistor. improvement about 23% was obtained without increasing power consumption. Additionally, circuit reduces dependence capacitance. chip 5 implemented Semi-Gaussian shaper 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
A simplified voltage reference topology with low power consumption based on MOS transistors in weak inversion operation is presented. 176 mV @ 27°C output a quiescent current of 2.7 μA 3.3 V and thermal coefficient 8.8 μV/°C the temperature range [-25; 100] °C had been achieved measurement results. The circuit fabricated AMS 0.35 μm C35B4 CMOS technology an active area 105 & <μm x 212 μm.
This paper presents a novel topology for LDO regulators, improving load regulation with very low quiescent current. The core of the circuit is made by operating pass transistor in linear region, achieving an area reduction above 90%, reducing gate capacitance and therefore loop response. proposed structure to improve based on transconductance cells current mirrors, allowing sink remaining energy compensation capacitor without affecting battery lifetime. design was developed AMS 0.35 mum...
This work presents the design and measured results of a 9-bit 10MS/s asynchronous SAR ADC at 0.5V supply voltage for Bluetooth Low Energy RF receivers. The was designed in 180nm CMOS technology using low-Vt transistors order to operate ultra-low voltage. A dynamic comparator bootstrapped circuit topologies, adequate low ADCs with power operation moderate speed are proposed this work. experimental consumption fabricated is 48μW 10MS/s, 8.55-bit ENOB FoM 13fJ/step.
The sPHENIX Time Projection Chamber Outer Tracker (TPOT) is a Micromegas based detector. It part of the experiment that aims to facilitate calibration Chamber, in particular correction time-averaged and beam-induced distortions electron drift. This paper describes detector mission, setup, construction, installation, commissioning performance during first year data taking.
This article presents the design and implementation of an API that delivers real-time promotional notifications to mobile devices based on their proximity shopping centers, calculated using Haversine formula. Developed in Laravel, determines whether a device is within 600-meter radius any registered center, such as Soriana, GranD, HEB, sends relevant information. The system uses Petri nets model asynchronous behavior, enabling efficient concurrency management between application API....
Abstract To operate the ALICE Time Projection Chamber in continuous mode during Run 3 and 4 data-taking periods of Large Hadron Collider, multi-wire proportional chamber-based readout was replaced with gas-electron multipliers. As expected, detector performance is affected by so-called common-mode effect, which leads to significant baseline fluctuations. A detailed study pulse shape new has revealed that it also ion tails. Since reconstruction data compression are performed fully online,...
This paper presents a small area CMOS current-steering segmented digital-to-analog converter (DAC) design used in RF transmitter stage for 2.45GHz Bluetooth applications. The current source strategy is based on an iterative scheme which variables are adjusted by simple way, satisfying the requirements, minimizing power consumption and reaching specifications. A theoretical analysis of static-dynamic requirements new layout DAC included. was designed implemented 0.35mm 4M2P technolyogy. Some...
A 180 nm TSMC CMOS 11 bit asynchronous successive approximation register Analog-to-Digital converter (SAR ADC) is developed for a breast cancer detection ultra wide-band transceiver. To improve the linearity, delay cell inside clock generator implemented, allowing larger settling time capacitor DAC. The implemented ADC occupies 0.1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and post-layout simulation results show that it...
In this work a low noise readout front-end for gaseous detectors with configurable sensitivity and peaking time is presented. The proposed topology supports positive/negative input charge polarity can be used TPC (Time Projection Chamber) systems Multi-Wire Proportional Chambers (MWPC) or Gas Electron Multiplier (GEM) technologies. configured 80ns, 160ns 300ns of 4mV/fC, 20mV/fC 30mV/fC via transmission gates. detector capacitance range where the circuit operates are 12pF to 25pF 30mV/fC,...
This paper presents an All-digital RF pulsed transmitter design with hardware complexity reduction techniques for FPGA implementation. A study of the operation frequency limitations parallel delta-sigma modulators (DSM) generating baseband signal is presented. Also, effect inserting zeros in DSM time-interleaved implementation on spectrum output discussed and compared to transmitters without techniques. Simulations all-digital Simulink <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This work presents the design of a 0.5V digital low dropout voltage regulator (DLDO) in 180nm CMOS technology for Dynamic Voltage Scaling applications. and leakage power consumption VLSI systems are effectively reduced by ultra-low operation, being that maximum energy efficiency is achieved at supply below 0.5V. Feedback-controlled analog LDO based on an operational amplifier can fail if it operates sub/near-threshold voltage. Digital LDOs have potential to replace circuits feedback loop...