A5010365065- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Advanced Data Storage Technologies
- MXene and MAX Phase Materials
- Integrated Circuits and Semiconductor Failure Analysis
- Magnetic properties of thin films
- Silicon Carbide Semiconductor Technologies
- Advancements in Photolithography Techniques
- Advanced Memory and Neural Computing
- Thin-Film Transistor Technologies
- Nanowire Synthesis and Applications
- Copper Interconnects and Reliability
- Force Microscopy Techniques and Applications
- Heusler alloys: electronic and magnetic properties
- Nanofabrication and Lithography Techniques
- Advanced MEMS and NEMS Technologies
- VLSI and Analog Circuit Testing
- ZnO doping and properties
- Block Copolymer Self-Assembly
- Advanced Surface Polishing Techniques
- Metal and Thin Film Mechanics
- Multiferroics and related materials
- Plasma Diagnostics and Applications
- 3D IC and TSV technologies
Nankai University
2023-2024
Chinese Academy of Sciences
2013-2023
Institute of Microelectronics
2014-2023
University of Chinese Academy of Sciences
2019-2020
Institute of Microelectronics
2015
Peking University
2011
Improving the endurance performance for hafnia-based ferroelectric thin films and devices is of considerable significance from both scientific technological perspectives. Here, we obtained robust ferroelectricity in Hf0.5Zr0.5O2 (HZO) without need confinement top electrodes by systematically optimizing conditions parameters post-deposition annealing (PDA) process. Compared with post-metallization (PMA) process, PDA found to markedly improve performance. In particular, wake-up-free HZO an...
We conducted a comprehensive investigation on the influence of TiN thickness and stress ferroelectric properties Hf0.5Zr0.5O2 thin films. top electrode layers with varying thicknesses 2, 5, 10, 30, 50, 75, 100 nm were deposited analyzed. It was observed that in-plane tensile in films increased electrode. This is expected to elevate film, consequently leading an enhancement polarization. However, effect behavior exhibited distinct stages: improvement, saturation, degradation. Our study...
In this study, novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. combination with structure advantage of conventional Si nanowires, proposed S-FinFETs provide better electrostatic integrity in channels than normal bulk-Si FinFETs or tri-gate devices rectangular trapezoidal fins. It is due to formation quasi-surrounding electrodes scalloping fins by a...
We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with metal gate length of 25 nm an effective channel less than 20 nm. The SPW features retrograde doping profile vertical direction drain/extension lateral direction. A novel process, called replacement spacer (RSG), is designed to avoid challenges patterning high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math...
Directed self-assembly (DSA), an emerging lithographic technique, has attracted increasing attention as a result of its advantages low cost, high throughput and convenient processing.
The magneto-electric coupling (MEC) effect has been considered an effective method for the voltages controlled magnetic anisotropy in traditional ferroelectric/ferromagnetic structures. Unlike perovskite ferroelectrics, ferroelectric hafnium-based oxides hold great potential use complementary metal oxide semiconductors (CMOS) circuit with advantages of CMOS compatibility and easy scaled-down lower leakage current. In this article, MEC effects PtCoRu/Hf0.5Zr0.5O2 (HZO) heterostructure have...
Hf0.5Zr0.5O2 (HZO) is a promising candidate for low-power non-volatile memory due to its nanoscale ferroelectricity and compatibility with silicon-based technologies. Stress oxygen vacancy (VO) are key factors that impact the of HZO. However, their combined effects have not been extensively studied. In this study, we investigated VO content on HZO thin films’ under different electrode stresses by using TiN tungsten (W) top electrodes controlling ozone dose time during deposition. The films W...
We propose and implement Stair Divided Scheme (SDS), a novel high density low cost staircase scheme for 3D NAND. In SDS, the stairs are divided into m zones in Y direction, thus only N/m needed X direction N control gates. further present photoresist (PR) consume model. The PR model fits result well. Based on model, we able to prove process efficiency of SDS. also show that SDS can improve integration higher bit density. Finally, find critical dimension (CD) stair zone shifts post etching....
In this work, we have investigated the evolution of line roughness from photoresist (PR) to poly-silicon gate etch based on composite SiO2/Si3N4/SiO2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe could be observed during patterning when PR pattern was directly transferred into ONO mask. Then, formation mechanisms were results effects decomposed oxygen radical generated SiO2 because ion bombardment and rough surface morphology that accelerates...
Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series device parameters on scaling is investigated. The high thin Fin structure tapered sidewall shows better performance than normal structure. punch through stop layer (PTSL) source drain extension (SDE) doping profiles carefully optimized. without SDE annealing larger drive current that due to Si crystal regrowth in amorphous after source/drain implantation....
Single drain select transistor (DSL) in 3D Flash memory may exhibit higher leakage as compared with DSL 2D NAND, because of worse subthreshold swing characteristics due to poly-Si channel. Select suppression is essential NAND Memory, consideration boosting potential and program disturbance. Compared single Si planner a novel dual cylindrical thin film proposed device suppress for good performance flash. And measurement approach also quantify inhibit case. The effect Vth modulation on...
This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for p-channel metal-oxide-semiconductor field-effect transistors fabricated by gate-last process. It is found that work function (WF) ALD titanium nitride/physical vapor titanium/chemical nitride (ALD TiN) MG in devices short channels larger than long channels. mainly results from different crystal orientations with gate lengths,...
A comprehensive simulation analysis method is proposed to improve the bottom select gate (BSG) transistor's Vth distribution by adopting under-channel implant in this work. L-shaped transistor used TCAT 3D NAND array. Bottom may exhibit broad distribution, due various lateral distances between cell string and common source, which an intrinsic challenge for TCAT-type flash In work, under channel scheme BSG optimization. Simulation result shows that, with optimized dose approach, less...
3D NAND is a great architectural innovation in the field of flash memory. The staircase for control gate unique and important process manufacturing NAND. employed to form electrical connection between contact. current method used measure dimension patterns is, however, not precise enough development state-of-the-art In this circumstance, an accurate measurement as-formed importance technical interest. paper, improved proposed meet requirement higher precision. By taking overlay into account,...
For the first time, a Gate-All-Around (GAA) Silicon Nanowire Transistor (SNWT) with one special nanowire channel-last (NCL) process technology on silicon (Si) substrate is reported. Different from traditional approach that channels are formed and released at initial steps of flow, NCL features release in high-k/metal gate-last during integration conventional bulk-Si FinFET. It provides stable way for introduction transistors FinFETs mass productions. The fabricated n-type effective diameter...
A novel three-step DRIE recipe with pulsed low frequency platen power of 380 KHz is proposed in this paper. The depassivation time/duty cycle and the etching step Bosh process are experimentally studied through silicon on glass (SOG) a micro-gyroscope. Experiments show that passivation time 2s, 2s/75% 4s/85% can effectively reduce notching effect anchors gyroscope while keep good sidewall verticality present no grass.
This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling the structure dimensions. The key performance, such as program/erase speed, vertical loss, and lateral migration under high temperature are intensively studied using Sentaurus simulator. Although channel radius is beneficial for operation speed improvement, it leads to retention challenge due leakage, especially enhanced loss through TPO. Scaling...
The ferroelectric field effect transistor (FeFET) is a very promising candidate for low-power and non-volatile memory. However, the co-existing of polarization interface charge trapping in FeFETs demonstrated many efforts have been made to eliminate this charge-trapping effect, which usually treated as deleterious effect. In contrast, we found that can play dominant role gates. work, verified ferroelectric/insulator could induce memory window main physical mechanism...
The impact of polysilicon thickness (THK-poly) and channel hole diameter (CHCD) on boosting potential during program inhibit has been studied with Sentaurus device simulator for three dimensional (3D) NAND memory. According to the distribution along channel, level thinner THK-poly is higher than that thicker one. Moreover, correlation between CHCD also depends THK-poly. In case 20nm THK-poly, strong dependence observed. When decreases 5nm, almost independent CHCD. Our results provide...
FinFETs with 20nm BEOL one generation improvement in performance and power efficiency has announced for mass production by leading IC companies. The processing details, however, have never been reported. In this talk, challenges of CMOS integration all-last gate stacks is presented based on our recent results. Special issues Fin the replacement (RMG) formation, RMG filling high-k/metal self-aligned contact (SAC) module will be discussed. It found that etching dummy behaves differently from...