A5000869304- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Nanowire Synthesis and Applications
- Advanced Surface Polishing Techniques
- Advancements in Photolithography Techniques
- Plasma Diagnostics and Applications
- Silicon Nanostructures and Photoluminescence
- Block Copolymer Self-Assembly
- Silicon Carbide Semiconductor Technologies
- Anodic Oxide Films and Nanostructures
- Integrated Circuits and Semiconductor Failure Analysis
- Ferroelectric and Negative Capacitance Devices
- Thin-Film Transistor Technologies
- Metal and Thin Film Mechanics
- Nanofabrication and Lithography Techniques
- Machine Learning in Materials Science
- Advanced Memory and Neural Computing
- Advanced Queuing Theory Analysis
- Ion-surface interactions and analysis
- Simulation Techniques and Applications
- Diamond and Carbon-based Materials Research
- Advanced Polymer Synthesis and Characterization
- Electrospun Nanofibers in Biomedical Applications
- Optical Coatings and Gratings
- Polymer crystallization and properties
Qingdao University of Technology
2019
Chengdu Technological University
2019
Institute of Microelectronics
2013-2018
Chinese Academy of Sciences
2013-2018
University of Chinese Academy of Sciences
2017
State Key Laboratory on Integrated Optoelectronics
2013
Beihang University
2006
In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> /metal FinFET flow implemented GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H <sub...
The large parasitic resistance has become a critical limiting factor to on current (I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> ) of FinFET and nanowire devices. Fully metallic source drain (MSD) process is one the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD fin-on-insulator (FOI) investigated extensively for first time. By forming Ni(Pt) silicide physically...
Sidewall damage caused in deep reactive ion silicon etch was investigated by varying cycle time, bias power, pressure and SF6 flow rate using the Bosch process a uniquely designed, inductively coupled plasma reactor. The effects of these parameters on profile sidewall angle were also studied for high density metal–insulator–metal capacitor structure. By choosing proper time 2 s, it observed that very sensitive to parameters. As power increased, increased gradually. Especially, at 500 W, dual...
In this study, novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. combination with structure advantage of conventional Si nanowires, proposed S-FinFETs provide better electrostatic integrity in channels than normal bulk-Si FinFETs or tri-gate devices rectangular trapezoidal fins. It is due to formation quasi-surrounding electrodes scalloping fins by a...
We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with metal gate length of 25 nm an effective channel less than 20 nm. The SPW features retrograde doping profile vertical direction drain/extension lateral direction. A novel process, called replacement spacer (RSG), is designed to avoid challenges patterning high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math...
A novel nanofabrication technique which can produce highly controlled silicon-based nanostructures in wafer scale has been proposed using a simple amorphous silicon (α-Si) material as an etch mask. SiO2 directly fabricated serve nanotemplates to transfer into the underlying substrates such silicon, germanium, transistor gate, or other dielectric materials form electrically functional and devices. In this paper, two typical nanoline nanofin have successfully by technique, demonstrating...
In this work, we have investigated the evolution of line roughness from photoresist (PR) to poly-silicon gate etch based on composite SiO2/Si3N4/SiO2 (ONO) multilayer hard mask structure using a capacitively coupled plasma etcher. A severe could be observed during patterning when PR pattern was directly transferred into ONO mask. Then, formation mechanisms were results effects decomposed oxygen radical generated SiO2 because ion bombardment and rough surface morphology that accelerates...
An aspect ratio (AR) dependent analytic model was developed for an inductively coupled plasma system. It can be used to quantitatively evaluate etch (ARDE), RIE lag and accurately predict depth of circular hole. The reciprocal average rate is a linear function AR only related initial at the top feature reaction possibility bottom feature. Initial extracted obtain accurate value not approximate value. Our experimental data in good agreement with proposed model.
Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series device parameters on scaling is investigated. The high thin Fin structure tapered sidewall shows better performance than normal structure. punch through stop layer (PTSL) source drain extension (SDE) doping profiles carefully optimized. without SDE annealing larger drive current that due to Si crystal regrowth in amorphous after source/drain implantation....
With the development of frontier technology in emerging semiconductor processes, self-assembling (SA) and directed self-assembly (DSA) block copolymers (BCPs) have attracted great attention from scientific researchers become promising candidates for advanced photolithography. Using an optimal coating baking process, highly ordered assembly morphologies (e.g., cylinder lamella) two BCPs thin films were obtained without additional topcoat material layer. Moreover, whole experimental study also...
We propose a CMOS-compatible top-down fabrication technique of highly-ordered and periodic SiO2 nanostructures using single amorphous silicon (α-Si) mask layer. The α-Si pattern is precisely transferred into the underlying substrate material with high fidelity by novel fabrication. It first time for film used as an etch to fabricate including nanoline, nanotrench, nanohole arrays. observed that can significantly reduce edge roughness achieve highly uniform smooth sidewalls. This behavior may...
In this work, two particular and interesting phenomena encountered in 14 nm gate mask etch including severe α-Si dummy top surface recess reversely tapered Si3N4 profiles have been observed for the first time by using 193 lithography. Due to 3D topography of FinFET devices, hard influences final profile, notch formation CD variation, which, turn, impacts electrical performance reliability devices. Therefore, fully understanding mechanism is a key avoid device degradation. It believed that...
In this paper, a fin-on-insulator (FOI) FinFET structure with metallic source and drain (MSD) HKMG-last processes was investigated extensively. FOI FinFETs demonstrated ten times of leakage current reduction compared conventional bulk using p-n junction. contrast to FinFETs, MSD demonstrate greatly improved control short channel effects (SCEs) (~47% DIBL ~32% SS reductions for 20-nm-Lg PMOS) FinFET. The drive ability transistor is increased about 30 full Ni(Pt) silicide process, up 547 μA/μm...
This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for p-channel metal-oxide-semiconductor field-effect transistors fabricated by gate-last process. It is found that work function (WF) ALD titanium nitride/physical vapor titanium/chemical nitride (ALD TiN) MG in devices short channels larger than long channels. mainly results from different crystal orientations with gate lengths,...
The Polyvinyl alcohol (PVA), polytetrafluorethylene (PTFE) and styrene-butadiene-rubber (SBR) were co-deposited with Ni(OH)2 respectively to serve as positive electrodes. Well adherent Ni (OH)2 deposits honeycomb coral structures obtained by doping PTFE SBR active materials of the electrode. effective surface area was significantly increased, so that specific capacitance electrode enhanced well. measurement on capacitances assembled C/Ni(OH) 2 capacitors indicates such electrodes doped can...
A novel type of high-χ block copolymer, polystyrene-block-polycarbonate (PS-b-PC), which contains an active -NH- group on the polymer backbone between PS and PC block, has been successfully synthesized. Vertical micro-phase separation can be achieved Si substrates with neutral-layer-free materials a pitch 16.8 nm. Water contact angle experiments indicate that have approximate surface energy values substrates. hydrogen bond mechanism proposed for formation periodic lamella-forming phase...
A novel CMP-less planarization technology featuring a SOG/LTO (Spin-on Glass /Low-Temperature Oxide) etchback method is presented to develop high-performance, low-cost, high-k/metal gate-last (HK/MG-last) integration process. For special PMD (Pre-Metal Dielectric) poly-open-planarization, new recessed three-step RIE (Reactive-Ion Etching) process developed in one chamber. This may replace general CMP with certain slurry. An etch-parameter study shows that an increase the reaction gas...