A5041018780- GaN-based semiconductor devices and materials
- Semiconductor materials and devices
- Silicon Carbide Semiconductor Technologies
- Ga2O3 and related materials
- Semiconductor Quantum Structures and Devices
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and interfaces
- Marine and coastal ecosystems
- Thermal Radiation and Cooling Technologies
- Ion-surface interactions and analysis
- Integrated Energy Systems Optimization
- Oceanographic and Atmospheric Processes
- Advanced Optical Sensing Technologies
- Quantum and electron transport phenomena
- Metal and Thin Film Mechanics
- Integrated Circuits and Semiconductor Failure Analysis
- Induction Heating and Inverter Technology
- Thermal properties of materials
- Environmental Monitoring and Data Management
- Radio Frequency Integrated Circuit Design
IMEC
2020-2024
University of Padua
2014-2022
Fraunhofer Institute for Microstructure of Materials and Systems
2022
Ghent University
2022
Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in industry silicon-based and currently faced with diminishing returns of performance versus cost investment. At material level, its high electric field strength electron mobility have already shown for frequency communications photonic applications. Advances on commercially viable large area substrates are now at the point where power conversion applications GaN cusp...
Power GaN transistors have recently demonstrated to be excellent devices for application in power electronics. The high breakdown field and the superior mobility of 2-dimensional electron gas allow fabricate with low resistive switching losses, that permit increase efficiency mode converters beyond 99 %. GaN-based are currently supposed adopted KW-range converters; 650 V already available on market, 1200 under development. During operation, can reach critical conditions, especially off-state...
This paper demonstrates and investigates the time-dependent vertical breakdown of GaN-on-Si power transistors. The study is based on electrical characterization, dc stress tests electroluminescence measurements. We demonstrate following original results: 1) when submitted to two-terminal (drain-to-substrate) stress, AlGaN/GaN transistors show a degradation process, which leads catastrophic failure devices; 2) time-to-failure follows Weibull distribution exponentially dependent voltage; 3)...
This paper presents an extensive investigation of the impact resistivity silicon substrate on vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different resistivities were submitted to combined DC characterization, step-stress experiments, electroluminescence (EL) analysis. The results described within this demonstrate that: 1) use a highly resistive can increase breakdown voltage transistors, due fact that drop...
In this paper, we present an in-depth study of the gate leakage mechanisms and correlated breakdown GaN-based power HEMTs with p-GaN gate, controlled by a Schottky metal/p-GaN junction. A detailed investigation process split geometry dependency is done. From study, propose that parasitic sidewall transistor present, which cause for degradation in gate. The has been substantiated TCAD simulation also novel method consisting EBIC measurements directly applied on cross section Based analysis...
In this work, we demonstrate enhancement-mode regrown p-GaN gate devices with high threshold voltage as well a robust forward time-dependent breakdown (TDGB) stability. The HEMTs are fabricated two different AlGaN barriers. Devices 16nm Al0.235 Ga0.765 N yield <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {TH}}$ </tex-math></inline-formula> of 1.5V and ( ) 2.7V is observed for 7nm along...
In this work, the gate current characteristics are investigated to explain threshold voltage shift in AlGaN/GaN high electron mobility transistors (HEMTs) with a p-GaN gate. First, intrinsic conduction mechanisms identified: low bias range (2.5 V <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ < {V}_{G} $ </tex-math></inline-formula> 4 V), thermionic emission (TE) dominates region, whereas higher (4 7...
This work addresses the impact of Mg activation anneal step and resulting acceptor concentration on channel mobility VT stability vertical MOSFETs. Increasing annealing time with N2 only ambient temperature O2 in is shown to be effective increasing concentration. When increased, degraded due a transition main scattering mechanism from Coulomb surface roughness scattering. Degradation on-state current maximum transconductance at high operating temperatures was linked bulk degradation drift...
This article presents a study on the improvement of gate robustness and reliability p‐GaN high‐electron‐mobility transistors (HEMTs) by doping profile engineering performing thermal treatment. The reduction p‐doping concentration at Schottky interface using graded magnesium (Mg) in layer introducing top Si‐GaN cap is proposed, combined with high‐temperature anneal step after patterning. results show that proposed approach enhances breakdown voltage, reduces leakage current, increases time to...
This paper investigates the time-dependent degradation of normally-off transistors with p-GaN gate submitted to constant voltage stress. Based on combined dc characterization and temperature-dependent analysis, we study dependence time-to-failure stress temperature device geometry. The results this analysis indicate that: (i) have a good stability, reaching 20 years lifetime 7.2 V bias; (ii) at higher voltages, failure is observed. Time-to-failure (TTF) depends exponentially voltage, while...
Abstract We present a first study of threshold voltage instabilities semi-vertical GaN-on-Si trench-MOSFETs, based on double pulsed, transient, and UV-assisted C – V analysis. Under positive gate stress, small negative th shifts (low stress) (high are observed, ascribed to trapping within the insulator at metal/insulator interface. Trapping effects eliminated through exposure UV light; wavelength-dependent analysis extracts de-trapping energy ≈2.95 eV. CV measurements describe distribution...
In this article, we present an in-depth high-temperature analysis of the long-term gate reliability in GaN-based power high-electron-mobility transistors (HEMTs) with p-type gate. Three different isolation process options, aimed at improving time-dependent breakdown (TDGB), are proposed and compared by means constant voltage stress tests performed forward biases, temperatures, geometries. particular, depending on bias temperature, event may occur along active area or through region. The...
This paper investigates the trapping mechanisms in gate-injection transistors (GITs) without and with a pdrain electrode, referred to as GITs Hybrid-Drain-embedded (HD-GITs), respectively, used inject holes reduce charge effects. We compare two sets of devices under both OFF-state semi-ON state, investigate role hot electrons favoring trapping. The analysis is based on combined pulsed characterization, transient measurements, electroluminescence (EL) characterization. demonstrate following...
TCAD modeling of the dynamic threshold voltage shift (hysteresis) occurring under fast sweeping characterization in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) is reported, to best our knowledge, for first time. Dynamic <inline-formula> <tex-math notation="LaTeX">${V}_{\text{TH}}$ </tex-math></inline-formula> hysteresis has been experimentally characterized different times, temperatures, and AlGaN barrier configurations. Then, simulations have carried out, reproducing...
This work reports the epitaxial growth of 8.5 µm-thick GaN layers on 200 mm engineered substrates with a polycrystalline AlN core (QST by QROMIS) for CMOS compatible processing vertical power devices. The stack contains 5 [Formula: see text]m thick drift Si doping density 2 × 1016 cm-3 and total threading dislocation 4 108 cm-2. layer requires fine-tuning conditions to keep wafer bow under control avoid formation surface defects. Diode test structures processed this achieved hard breakdown...
The forward bias gate leakage current and breakdown voltage are important properties of p-GaN high-electron-mobility transistors (HEMTs). An engineered doping profile in the layer results a higher lower current. use such technique puts additional requirements on compact models that used for these HEMTs. accurate model is needed, which considers change devices. This article reviews relationship between drops at different junctions structure (i.e., metal/p-GaN Schottky junction p-GaN/AIGaN/GaN...
We propose a technique to evaluate the time-dependence of threshold voltage instabilities in GaN-based normally-off transistors under positive gate bias. More specifically: (i) for first time we experimentally Vth shift wide window (from 10 s 100 s), as function temperature. (ii) study existence two dominant trapping processes, having different time-kinetics. (iii) process, occurring initial s, leading shift, and ascribed injection electrons from 2DEG towards AlGaN barrier; (iv) second only...
The aim of this work is to investigate the breakdown mechanisms layers constituting vertical buffer GaN-on-Si HEMTs; in addition, for first time we demonstrate that field AlN nucleation layer grown on a silicon substrate equal 3.2 MV/cm and evaluate its temperature dependence. To aim, three samples, obtained by stopping epitaxial growth GaN Silicon stack at different steps, are studied compared: Si/AlN, Si/AlN/AlGaN, full up Carbon doped layer. current-voltage (IV) characterizations...
A combined experimental/simulation analysis has been performed to study the gate reliability of GaN-HEMTs with p-type under pulse stress conditions. Results show that time-dependent breakdown (TDGB) can be determined by two factors: i) total ON-time during which device is subjected a positive bias before failure; ii) number pulses, hence switching phases from OFF- ON-State and vice versa. The severity degradation ascribed transition depends on OFF-time (tOFF) time (tTR = tRISE tFALL). In...
This paper presents an extensive analysis of the impact substrate and buffer properties on performance breakdown voltage E-mode power HEMTs. We investigated thickness, resistivity miscut angle, by characterizing several wafers means DC pulsed measurement. The results demonstrate that: (i) silicon strongly impacts vertical leakage current. In fact, highly resistive substrates may partly deplete under high bias, thus limiting total potential drop epitaxial layers. As a consequence, IV plots...
We propose to use a bilayer insulator (2.5 nm Al2O3 + 35 SiO2) as an alternative conventional uni-layer (35 nm), for improving the performance and reliability of GaN-on-Si semi vertical trench MOSFETs. This analysis has been performed on test vehicle structure module development, which limited OFF-state performance. demonstrate that devices with dielectric present superior characteristics than those uni-layer, including: (i) gate leakage two-orders magnitude lower; (ii) 11 V higher off-state...