Doo-Hyun Kim

ORCID: 0000-0003-3153-5625
Publications
Citations
Views
---
Saved
---
About
Contact & Profiles
Research Areas
  • Multimedia Communication and Technology
  • Engineering Applied Research
  • Advanced Combustion Engine Technologies
  • Semiconductor materials and devices
  • Fire Detection and Safety Systems
  • Education, Safety, and Science Studies
  • Advanced Data Storage Technologies
  • Combustion and flame dynamics
  • Mobile Agent-Based Network Management
  • Internet of Things and Social Network Interactions
  • Real-Time Systems Scheduling
  • Peer-to-Peer Network Technologies
  • Video Coding and Compression Technologies
  • Risk and Safety Analysis
  • Diverse Approaches in Healthcare and Education Studies
  • Energy and Environmental Systems
  • Advancements in Semiconductor Devices and Circuit Design
  • Electrical Fault Detection and Protection
  • Marine and Coastal Research
  • Advanced Vision and Imaging
  • Real-time simulation and control systems
  • Technology and Data Analysis
  • Image and Video Quality Assessment
  • IPv6, Mobility, Handover, Networks, Security
  • Network Time Synchronization Technologies

Samsung (South Korea)
2012-2025

University of Michigan–Dearborn
2021-2024

Chungbuk National University
2011-2024

Inserm
2024

Centre de Recherche en Cancérologie de Lyon
2022-2024

Centre National de la Recherche Scientifique
2024

Université Claude Bernard Lyon 1
2024

Konkuk University
2008-2021

Hanyang University
2009-2020

Hongik University
2018-2020

In this work, we present a true 3D 128 Gb 2 bit/cell vertical-NAND (V-NAND) Flash product for the first time. The use of barrier-engineered materials and gate all-around structure in V-NAND cell exhibits advantages over <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$1 \times$</tex></formula> nm planar NAND, such as small Vth shift due to coupling narrow natural distribution. Also, negative...

10.1109/jssc.2014.2352293 article EN IEEE Journal of Solid-State Circuits 2014-09-17

A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated loading and variations are discussed. To enhance performance, reverse read scheme variable-pulse presented to cope nonuniform characteristics. For improved dual state machine architecture proposed achieve optimal timing for BL WL, respectively. Also, maintain robust IO driver strength against PVT variations, an embedded ZQ calibration technique...

10.1109/jssc.2016.2604297 article EN IEEE Journal of Solid-State Circuits 2016-10-24

A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested resolve issues. For performance enhancement, novel program method hiding two-page data loading time This paper also discusses an electrical annealing improving reliability characteristic by removing holes in shallow traps. In addition, valley tracking read for reducing timing overhead at retry introduced fast finding...

10.1109/jssc.2017.2731813 article EN IEEE Journal of Solid-State Circuits 2017-08-15

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as shorter tPROG, lower power consumption and higher endurance. For many years, every effort has been made shrink die size cost improve performance. However, the previously used node-shrinking methodology is facing challenges due increased cell-to-cell interference patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking...

10.1109/jssc.2015.2474117 article EN IEEE Journal of Solid-State Circuits 2015-09-21

In the past few years, various 3D NAND Flash memories have been demonstrated, from device feasibility to chip implementation, overcome scaling challenges in conventional planar [1-3]. The difficulties include shrinking cell and increasing manufacturing costs due quadruple patterning extreme ultraviolet lithography, motivating development of next-generation node beyond 16nm-class [4]. this paper, as a new memory with lower cost superior scalability, we present true 128Gb 2b/cell vertical-NAND...

10.1109/isscc.2014.6757458 article EN 2014-02-01

The advent of emerging technologies such as cloud computing, big data, the internet things and mobile computing is producing a tremendous amount data. In era storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, power operation. SSDs employing 3D NAND promising to meet these requirements. Since introduction technology marketplace in 2014 [1], memory array size has nearly doubled every year [2,3]. To continue scaling...

10.1109/isscc.2017.7870331 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2017-02-01

Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since introduction 3D technology in 2014 [1], V-NAND believed to be a successful alternative planar NAND quickly displacing SSD market, due its performance, reliability, cost competitiveness. has also eliminated cell-to-cell interference problem by forming an atomic layer charge trapping [2], which enables further scaling. However, etching required...

10.1109/isscc.2016.7417941 article EN 2022 IEEE International Solid- State Circuits Conference (ISSCC) 2016-01-01

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made shrink die size cost improve performance. However, the previously used node-shrinking methodology is facing challenges due increased cell-to-cell interference patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking...

10.1109/isscc.2015.7062960 article EN 2015-02-01

10.1016/j.fuel.2018.04.112 article EN publisher-specific-oa Fuel 2018-05-12

In this work, we present a 3D 128Gb 2bit/cell vertical-NAND (V-NAND) Flash product. The use of barrier-engineered materials and gate all-around structure in the V-NAND cell exhibits advantages over 1xnm planar NAND, such as small Vth shift due to coupling narrow natural distribution. Also, negative counter-pulse scheme realizes tightly programmed order reduce effect large WL coupling, glitch-canceling discharge pre-offset control is implemented. Furthermore, an external high-voltage supply...

10.1109/nvmts.2014.7060840 article EN 2014-10-01

We investigated the variation of electrical performances solution-processed zinc tin oxide thin-film transistors (ZTO TFTs) when their channel layer was exposed to ambient gases at room temperature. During our research, we observed that adsorption H2O on backchannel surface can act as an electron trap and/or donor, depending amount H2O. In addition, found abnormal behavior seen in TFTs caused by different rates adsorption/desorption. Finally, instability characteristics ZTO atmosphere easily...

10.1143/apex.5.021101 article EN Applied Physics Express 2012-01-19

Convolutional neural networks (CNNs) have greatly improved image classification performance. However, the extensive time required for owing to large amount of computation involved, makes it unsuitable application low-performance devices. To speed up classification, we propose a cached CNN, which can classify input images based on similarity with previously images. Because feature maps extracted from CNN kernel represent intensity features, similar be classified into same class. In this...

10.3390/app9010108 article EN cc-by Applied Sciences 2018-12-29
Coming Soon ...