A5034017479- Semiconductor materials and devices
- Silicon and Solar Cell Technologies
- Semiconductor materials and interfaces
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Surface Polishing Techniques
- Thin-Film Transistor Technologies
- Non-Destructive Testing Techniques
- Numerical methods in engineering
- Machine Learning in Materials Science
- VLSI and Analog Circuit Testing
- Advanced MEMS and NEMS Technologies
- Acoustic Wave Resonator Technologies
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Radiation Effects in Electronics
- Advanced Materials and Mechanics
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Electron Microscopy Techniques and Applications
- Muon and positron interactions and applications
- Parallel Computing and Optimization Techniques
- 3D IC and TSV technologies
- Electron and X-Ray Spectroscopy Techniques
- Metallic Glasses and Amorphous Alloys
- Metal Forming Simulation Techniques
- Electronic Packaging and Soldering Technologies
Samsung (Japan)
2023-2024
Samsung (South Korea)
2018
CEA Grenoble
2014-2017
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2014-2017
CEA LETI
2015-2017
Université Grenoble Alpes
2014-2017
Institut polytechnique de Grenoble
2014-2017
IMDEA Materials
2015-2016
STMicroelectronics (France)
2015-2016
3D sequential integration requires top FETs processed with a low thermal budget (500–600°C). In this work, high performance temperature FDSOI devices are obtained thanks to the adapted extension first architecture and introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD nMOS: SiC:P RSD). This demonstration n p shows that activated device can match state-of-the-art process (above 1000°C).
Using a combination of domain decomposition, massive parallelization and dimensionality reduction, full chip-size stress simulation flow was developed. By application shell elements in the Finite Element Method (FEM) framework, prediction distribution Flash memory die (area about 1 cm²) back end line (BEOL) metallization layers with nanometer scale precision becomes possible within half day. Model calibration for several product generations allowed more than 90 percent accuracy crack defect...
Abstract Strain boosters are an effective way to improve performances in advanced CMOS FDSOI devices. Hole mobility is higher pFETs with compressive channels. Meanwhile, electron for nFETs tensile We present alternative technique blanket sSOI substrates. The efficiency of the “Strained Silicon by Top Recrystallization Amorphized SiGe on SOI” has been previously successfully demonstrated SOI (+ 1.6 GPa strain achieved). Here we demonstrate a simple and efficient STRASS module integration...
An electro-thermal resistive switching model based on O-Frenkel pairs is presented. This relies partial differential equations and used to simulate reset set mechanisms for HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based RRAM devices starting from an existing conductive filament. First simulations indicate that the can fairly reproduce experimental ON OFF resistances.
Coupled effects of substrate orientation and germanium concentration during silicon-germanium Solid Phase Epitaxial Regrowth (SPER) is analyzed through lattice kinetic Monte Carlo simulations. Atomistic events depending on the bonding environment allow to replicate alloying SPER velocity (100) substrates. The model then used draw predictions regrowth anisotropy in SiGe. Whereas Ge increase leads a well-established rate increase, whatever orientation, moving away from decrease caused by an...
The solid phase epitaxial regrowth (SPER) of SiGe alloys has been studied using atomistic simulation techniques. Molecular Dynamics (MD) simulations reproduce the recrystallization process amorphous structures created in two different ways: introducing atoms at random positions according to crystalline density and carefully relaxing structure; a bond switching algorithm by means ab initio. Activation energies are confronted, first method is validated as an efficient way generate...
A new dynamical space partitioning method is presented in a parallelized lattice kinetic Monte Carlo (kMC) simulator to overcome the loss of parallel efficiency found other kMC simulators. The simulation cell allows better load balancing through all threads hence reducing time consuming events during simulation. evaluated against both hypothetical and real cases. In cases, minimal differences between serial simulations are found. code optimizations may be needed further improve efficiency.