A5073683355- Semiconductor materials and devices
- 3D IC and TSV technologies
- Silicon and Solar Cell Technologies
- Semiconductor materials and interfaces
- Thin-Film Transistor Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Interconnection Networks and Systems
- Silicon Carbide Semiconductor Technologies
- Silicon Nanostructures and Photoluminescence
- GaN-based semiconductor devices and materials
- VLSI and FPGA Design Techniques
- Fluid Dynamics and Thin Films
- Advancements in Photolithography Techniques
- Copper Interconnects and Reliability
- Embedded Systems Design Techniques
- Electron and X-Ray Spectroscopy Techniques
- Adhesion, Friction, and Surface Interactions
- Advanced Materials Characterization Techniques
- Advanced ceramic materials synthesis
- Electronic Packaging and Soldering Technologies
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Electronic and Structural Properties of Oxides
- X-ray Spectroscopy and Fluorescence Analysis
STMicroelectronics (France)
2016-2024
STMicroelectronics (Czechia)
2022
Commissariat à l'Énergie Atomique et aux Énergies Alternatives
2014-2018
Université Grenoble Alpes
2014-2018
CEA LETI
2014-2018
CEA Grenoble
2014-2018
Institut polytechnique de Grenoble
2014-2017
Institut de Microélectronique, Electromagnétisme et Photonique
2015
European Automobile Manufacturers Association
2014
3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices unique connecting via density above million/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This results in increased no extra cost associated to transistor scaling, while benefiting from gains power and performance thanks wire-length reduction. technology leads high top transistors Thermal Budgets (TB) compatible bottom MOSFET integrity. Key...
3D Sequential Integration (3DSI) with ultra-small contact pitch (<;100nm) offers new partitioning options at fine granularities. This paper reviews potential applications ranging from computing to sensor interface and gives an update on 3DSI device development. Low-temperature processing techniques have made great progress High Performance (HP) digital stacked FETs for application can be achieved a 500°C Thermal Budget (TB). In addition, ULK/metal lines capable of withstanding this TB used...
For the first time, a full 3D CMOS over CoolCube™ integration is demonstrated with top level compatible state of art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional inverters either PMOS NMOS on are highlighted. Furthermore, Si layer transfer above 28nm W Metal 1 an industrial short loop return in front end environment presented, confirming compatibility integration.
Compared with TSV-based 3D ICs, monolithic or sequential ICs presents "true" benefits of going to the vertical dimension as stacked layers can be connected at transistor scale. The high versatility this technology is evidenced via several examples requiring small contact pitch. Monolithic shown enable substantial gain in area and performance compared planar without scaling node. This paper summarizes technological challenges concept: it offers a general overview potential solutions obtain...
For the first time maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure stability in Sequential 3D (CoolCube™) integration. We highlight no degradation Ion/Ioff trade-off up 550°C. Thanks both metal gate work-function especially on short devices and silicide improvement, top temperature could be relaxed 500°C. Laser anneal then considered as a promising candidate for junctions activation. Based in-depth...
Monolithic or sequential 3D Integration is a powerful technological enabler for actual IC design as the stacked layers can be connected at transistor scale. This paper reviews opportunities brought by M3DI and highlights applications benefiting from this small contact pitch. It also presents challenges of concept offers general overview potential solutions to obtain high performance low temperature top while keeping bottom MOSFET integrity.
In this paper we present a methodology allowing an emulated-3D two tiers physical implementation of any design using 2D commercial tools. Place and Route is achieved through similar steps as required by designs: pre clock tree synthesis (including placement), routing; to which added folding step in order emulate the 3D placement. Routing both parallel inter-tier metal layers made possible modifying input files Our study covers power supply network on tiers, forbidden via active placement...
To set up specification for 3D monolithic integration, the first time, thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on to mimic budget associated top layer processing. Degradation silicide treatments beyond 400°C identified as main responsible degradation PMOS devices. For NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds this effect. By optimizing both...
In this paper we present a methodology allowing an emulated-3D two tiers physical implementation of any design using 2D commercial tools. Place and Route is achieved through similar steps as required by designs: pre clock tree synthesis (including placement), routing; to which added folding step in order emulate the 3D placement. Routing both parallel inter-tier metal layers made possible modifying input files Our study covers power supply network on tiers, forbidden via active placement...
By stacking transistor levels on each other sequentially, monolithic 3D integration appears to be an alternative solution scaling. taking fully advantages of the vertical dimension, circuit partitioning at scale is then possible. This papers gives different opportunities offered by such technology and summarizes technological challenges that raises from this concept. A general overview techniques create active layer above a bottom level presented. Direct bonding SOI wafer clearly currently...
3D VLSI with a CoolCube™ monolithic integration flow allows vertically stacking several layers of devices unique connecting via density above tens million/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This results in increased and gains power performance thanks to wire-length reduction without the extra cost associated transistor scaling. In addition saving, this true opens perspectives terms heterogeneous integration. We will...
In this paper, the recent advances in low temperature process view of 3D VLSI integration are reviewed. Thanks to optimization each modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, top layer thermal budget fabrication has been decreased order satisfy requirements for integration.
This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads an improvement gate stack reliability below 525°C (iii) state-of-the-art SiOCH ULK iBEOL up 550°C 5h W metal lines. A integration thus proposed match the windows of bottom...
For the first time thermal stability of a new fluorine-free (F-free) W barrier coupled with interconnections enabling 22% line 1 resistance improvement is evaluated in view 3D VLSI integration. Integrated ULK, no nor lateral capacitance degradation observed up to 550°C 5h while preserving good reliability. additional TEOS/W demonstrated 600°C 2h. Both types interconnection stacks have been successfully integrated on devices 28nm design rules and show similar performance for MOSFETs Ring...
Design of conventional 2D integrated circuits is becoming more and challenging as we strive to keep on following Moore's law. Cost, thermal behavior, multiple patterning, increasing number design rules, transistor characteristics, variability back end properties coupled with a constant need for higher integration functions / peripherals are creating an increasingly complex equation solve designers. Moving the next node taking advantage technology now far from being straightforward time...
While the 3D sequential process is still under development, electrical influence of specific for bottom tier needs to be studied. As another MOS transistor layer fabricated on top one, contamination risk and thermal stability issues appear, thus requiring adaptation conductors/dielectrics intermediate Back-End Of Line (iBEOL) processing. materials differ from usual copper/low-k, it necessary study how standard cells characteristics will affected. We modeled different descriptions iBEOL in...
3D VLSI technology based on CoolCube <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">™</sup> process offers ultra-high density of integration with up to 10 xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> Vias (3D-V) per mm xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> offering gate level capability. For stability and wide range temperature compliancy, Intermediate Back End Line (IBEOL) is targeted be made Tungsten lines in a SiO <sub...
Original approach to detect and quantify carbon atoms located in different chemical states SiGeC films using X-ray photoelectron spectroscopy.
In 3D sequential integration, the top transistor thermal budget must be reduced to preserve bottom MOSFET performance. order relax this limitation, stability of level increased, especially for silicide. that purpose, Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.9</sub> Co xmlns:xlink="http://www.w3.org/1999/xlink">0.1</sub> alloy is proposed replace current xmlns:xlink="http://www.w3.org/1999/xlink">0.85</sub> Pt...
Abstract 3D sequential integration is a promising alternative to conventional scaling down approach: by stacking transistors level on top of each other, benefits device density and performance are achieved. However, although the thermal processing currently restricted in order avoid bottom CMOS degradation, it has been highlighted that Ni 0.80 Pt 0.10 silicide source/drain (S&D) contact remains most sensitive element budget, especially raised Si 0.7 Ge 0.3 :B S&D for pMOS...
This work highlights recent advances in 3D VLSI integration. A review of low temperature process modules development such as junctions, spacers and salicidation is presented. Finally, for the first time, a full CMOS over integration on 300mm wafers demonstrated with top level compatible state art high performance FDSOI (Fully-Depleted Silicon On Insulator) requirements High-k/metal gate or raised source drain.